Cu3Sn Via Metallization for Low-Temperature 3D Interconnect Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D-integrated electrical devices face challenges in forming reliable electrical interconnects at low temperatures due to high-temperature annealing requirements, which can degrade temperature-sensitive materials and cause thermal expansion issues, leading to cracking and bond failures.
Innovation Solution
The use of a copper-tin intermetallic compound, Cu3Sn, as an interconnect material, formed through low-temperature solid-state diffusion between deposited Sn and Cu layers, enabling fusion bonding at temperatures below 200°C, and a method to form void-free Cu3Sn interconnects by depositing Sn first and then Cu, allowing Kirkendall voids to be removed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-temperature annealing (≥300°C) is used for fusion bonding of vertical metal interconnects, then reliable electrical connection is achieved, but temperature-sensitive materials (e.g., HgCdTe) are degraded and thermal expansion mismatches cause cracking and bond failures
Solution Approach 1:
The patent changes the bonding temperature parameter from conventional high temperatures (≥300°C) to low temperatures (≤200°C, preferably 100-150°C) by using Cu3Sn intermetallic compound interconnects, which have suitable diffusion properties at low temperatures to enable fusion bonding without degrading temperature-sensitive materials or causing thermal expansion damage
Solution Approach 2:
The patent uses Cu3Sn intermetallic compound as a composite material that combines the advantages of copper (high electrical conductivity) and tin (low melting point, good diffusion properties), enabling low-temperature fusion bonding while maintaining reliable electrical connections and compatibility with temperature-sensitive materials like HgCdTe
2Temperature
If Cu3Sn interconnects are formed through solid-state diffusion between Sn and Cu layers, then low-temperature fusion bonding (≤200°C) is enabled, but Kirkendall voids may form during the diffusion process
Solution Approach 1:
The patent applies preliminary action by depositing a Cu layer on the Sn layer before the diffusion process begins. This preliminary layer configuration ensures that during solid-state diffusion, the Kirkendall voids form within the Cu layer rather than at the Sn-Cu interface, allowing for better void management and maintaining interconnect structure quality at low bonding temperatures
Solution Approach 2:
The patent converts the harmful effect of Kirkendall void formation into a beneficial outcome by strategically positioning the voids within the Cu layer through controlled deposition sequences. The voids that would normally compromise structural integrity are instead contained within the Cu layer, allowing the Sn-Cu diffusion process to proceed at low temperatures while maintaining acceptable interconnect quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of temperature-sensitive materials like HgCdTe in 3D-integrated devices by providing reliable, corrosion-resistant, and conductive interconnects with enhanced thermal expansion, facilitating low-temperature hybrid bond processing and minimizing mechanical weakening.
Implementation Method 1
heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu3Sn interconnect in the via hole
Implementation Method 2
heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together
Data Source
AI summary
A Cu3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.