3D Memory Via Formation for Concurrent CuA Etch-Stop Penetration
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Solution Overview
Problem
Existing 3D memory device fabrication technologies require extra steps and resources to form vias that penetrate the etch stop layer, leading to increased fabrication costs and reduced density due to the need for additional masks and area usage.
Innovation Solution
A complementary metal-oxide-semiconductor (CMOS) under array (CuA) process that concurrently forms vias to penetrate the etch stop layer in both peripheral and memory areas, allowing direct electrical and physical coupling to drivers and reducing the need for interconnect structures within the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extra vias are formed to penetrate the etch stop layer in existing fabrication processes, then electrical connection is achieved, but fabrication cost increases and density decreases
Solution Approach 1:
The patent merges the formation of vias in the memory area and peripheral area into a single concurrent process step. The via formation is combined with the etch stop layer penetration in one operation, eliminating the need for separate via formation steps and reducing overall fabrication complexity and cost.
Solution Approach 2:
The etch stop layer serves multiple functions: it acts as a barrier during fabrication, defines the boundary between memory and peripheral areas, and enables concurrent via formation. By making the etch stop layer multi-functional, the patent eliminates the need for additional masks and reduces fabrication steps.
2Reliability
If extra vias and interconnect structures are used in existing fabrication processes, then electrical coupling is achieved, but area efficiency decreases
Solution Approach 1:
The patent merges via formation with etch stop layer penetration in a single process step. This concurrent formation eliminates the need for separate interconnect structures, reducing area consumption while maintaining electrical coupling between memory cells and peripheral circuits.
3Ease of manufacture
If extra masks and fabrication steps are used, then via formation is achieved, but productivity decreases
Solution Approach 1:
The patent combines via formation and etch stop layer penetration into one concurrent process step, eliminating the need for additional masks and fabrication steps. This integration directly improves productivity by reducing the total number of process steps required.
Data Source
AI summary
Memory devices and a method of fabricating memory devices are disclosed. In one aspect, the method includes forming a plurality of first transistors in a first area and a plurality of second transistors in a second area and forming a stack over the second area. The method includes forming a memory array portion and an interface portion through the stack. The memory array portion includes memory strings and the interface portion includes first conductive structures extending along a lateral direction. The method further includes simultaneously forming second conductive structures in the first area and forming third conductive structures in the second area. The second conductive structures each vertically extend to electrically couple to at least one of the first transistors, and the third conductive structures each vertically extend through one of the memory strings to electrically couple to at least one of the second transistors.