Semiconductor CUB Structure Capacitor Insulating Layer Segmentation
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Solution Overview
Problem
The manufacturing of semiconductor devices with a capacitor under bit line (CUB) structure faces challenges in forming deep contact holes due to the increased thickness of the insulating layer, which also leads to higher coupling capacitance between the bit line and the upper electrode.
Innovation Solution
A method involving the formation of multiple insulating layers and conductive studs, with specific etching and damascene processes, to create contact holes and trenches that allow for the reduction of coupling capacitance while enabling the formation of deep contact holes, including the use of a damascene process for forming Cu studs and a dual damascene process for placing bit lines and wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of the insulating layer between the upper electrode and bit line is increased to reduce coupling capacitance, then the coupling capacitance is reduced, but the depth of contact holes is increased making them difficult to form
Solution Approach 1:
The patent divides the insulating layer into multiple segments: a first insulating layer with greater thickness between the upper electrode and bit line (to reduce coupling capacitance), and a second insulating layer with lesser thickness above the first insulating layer. This segmentation allows the contact holes to pass through the thinner second insulating layer more easily while still achieving sufficient isolation from the bit line through the thicker first insulating layer.
2Ease of manufacture
If a simple capacitor fabrication process is used for CUB structure, then the manufacturing process is simpler, but the coupling capacitance between upper electrode and bit line increases
Solution Approach 1:
The patent applies local quality by creating a first insulating layer with specifically greater thickness in the region between the upper electrode and bit line, while the second insulating layer above it has lesser thickness. This localized thickness variation针对性地 reduces coupling capacitance where needed without unnecessarily increasing the overall insulating layer thickness, maintaining manufacturing feasibility.
Data Source
AI summary
Provided is a method of manufacturing a semiconductor device having a capacitor under bit line (CUB) structure capable of increasing a gap between a bit line in a cell area and an upper plate of a capacitor, reducing coupling capacitance therebetween, and forming deep contacts in a logic area. A capacitor including a lower electrode, a dielectric material layer, and an upper electrode is formed in an opening of a first insulating layer for exposing a first part of a semiconductor substrate in a cell area. A second insulating layer is formed on the first insulating layer. The first and second insulating layers are etched. First and second contact plugs are formed in first and second contact holes for exposing second and third parts in the cell area and the logic area. A third insulating layer including first through third conductive studs is formed on the second insulating layer. A fourth insulating layer including a bit line and first and second wires contacted with the first through third conductive studs is formed.