CubeSat SSDR with Independent NAND Power Control
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Solution Overview
Problem
Current data recorder solutions for CubeSats and SmallSats face challenges in harsh radiation environments, lacking high reliability, high-speed data rates, and compact form factors, which are essential for efficient data storage and processing in space missions.
Innovation Solution
A miniaturized (3.5 in.×3.5 in.) solid state data recorder (SSDR) card with a field programmable gate array (FPGA) design, radiation-tolerant components, and advanced error correction mechanisms, enabling high-density, high-speed data storage and processing in a compact form factor suitable for harsh radiation environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If commercial CubeSat data recorder designs are used, then cost and miniaturization are reduced, but reliability and radiation tolerance deteriorate
Solution Approach 1:
The data recorder is divided into independent functional modules including FPGA-based control logic, multiple NAND flash memory banks with independent power control, error correction units, and radiation tolerance circuits. This modular segmentation enables targeted optimization of each component for radiation hardness while maintaining overall system reliability without excessive complexity.
Solution Approach 2:
The system employs a composite architecture combining radiation-hardened FPGA logic with commercial off-the-shelf (COTS) NAND flash memory banks. This composite approach integrates components with different radiation tolerance characteristics, achieving overall system reliability through error correction codes and redundant storage structures while managing complexity through standardized interfaces.
2Reliability
If larger form-factor reliable storage options are selected, then reliability improves, but volume and mass constraints are violated
Solution Approach 1:
Multiple NAND flash memory banks are arranged in a compact nested configuration within the 3.5 in.×3.5 in. card form factor. The independent power control circuits and error correction modules are integrated into the same substrate, enabling high-density reliable storage without increasing volume beyond CubeSat constraints.
Solution Approach 2:
The design transitions from planar component layout to three-dimensional stacking of memory banks and control circuits. Multiple layers of NAND flash are vertically arranged with interconnect structures routing signals between layers, achieving high storage density and reliability within the limited 3.5 in.×3.5 in. footprint while maintaining radiation tolerance through redundant architectures.
3Reliability
If redundant memory systems are implemented, then reliability improves, but volume and mass increase
Solution Approach 1:
Multiple NAND flash memory banks are merged into a unified storage system with shared control logic implemented in the FPGA. The independent power control feature allows selective activation of banks, enabling redundancy without requiring all banks to be simultaneously active. This combining approach achieves reliability through fault tolerance while minimizing the quantity of active memory substance at any given time.
Solution Approach 2:
The system implements wear-leveling algorithms that dynamically discard data from memory banks reaching their write endurance limits and recover by redistributing data to fresher banks. This extends the operational lifetime of the redundant memory system without requiring additional memory capacity, maintaining reliability while optimizing the quantity of active storage substance.
4Productivity
If high-speed data rates are implemented, then data throughput improves, but power consumption increases
Solution Approach 1:
The independent power control feature enables periodic activation of NAND flash banks based on data throughput requirements. During high-speed data acquisition, multiple banks are activated simultaneously to sustain high throughput. During low-activity periods, banks are placed in low-power sleep modes, reducing overall power consumption while maintaining the capability for high-speed operation when needed.
Solution Approach 2:
The system dynamically adjusts the number of active NAND flash banks and their operational modes based on real-time data throughput demands. The FPGA control logic monitors data flow rates and activates additional banks only when high-speed storage is required, optimizing the balance between data throughput and power consumption throughout the mission lifecycle.
Data Source
AI summary
The present invention relates to a single-board solid state data recorder (SSDR) card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, which includes: a field programmable gate array (FPGA): a plurality of NAND storage banks of non-volatile NAND Flash storage, the plurality of NAND storage banks which store operational data, each of which is controlled by a NAND Flash controller which controls the signaling of the plurality of NAND storage banks and reading and writing to the plurality of NAND storage banks; and a plurality of SpaceWire nodes and a plurality of multi-gigabit transceivers which command the SSDR card and read/write data to the SSDR card; wherein the plurality of NAND Flash memory banks is independently controlled and independently powered.