Cubic LDPC Encoder Using Extra Check Rows to Cut Matrix Complexity

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Solution Overview

Problem

Existing low-density parity-check (LDPC) code generators face complexity and resource-intensive challenges due to large matrix operations required for error correction, particularly in converting information bits into check bits, which can be costly in terms of time and hardware resources.

Innovation Solution

The proposed method involves generating check codes with a greater number of check operations than check bits, utilizing a parity check matrix with additional check rows to provide more constraints for improved error correction, reducing the complexity of matrix operations and resource requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large matrix-vector multiply operation is used to convert information bits into check bits, then error correction capability is improved, but computational complexity and hardware resource requirements increase significantly

Engineering Contradiction:
Improveerror correction capabilityVSAvoidmatrix operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the large N×K generator matrix into smaller sub-matrices, specifically organizing it as a systematic matrix where the first K columns form an identity matrix and the remaining N-K columns contain the check bit generation coefficients. This segmentation allows the encoding operation to be performed in two simple steps: copying information bits to their corresponding positions and computing check bits using only the non-systematic portion, thereby reducing computational complexity while maintaining error correction capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of using the traditional large matrix-vector multiplication approach that requires O(NK) operations, the patent inverts the approach by using the parity check matrix H to define the code structure. The generator matrix G is derived from H such that GH=0, allowing encoding to be performed through simple bitwise operations and additions rather than full matrix multiplication, thus reducing hardware resource requirements

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If a large matrix-vector multiply operation is used to convert information bits into check bits, then check bits can be generated, but time and hardware resources required for the operation increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidencoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the encoding process into two independent stages: (1) placing information bits directly into the code word at positions corresponding to the identity matrix columns, and (2) computing check bits using only the M×K non-systematic sub-matrix where M=N-K. This segmentation reduces the number of multiplication operations from NK to MK, significantly decreasing encoding time while preserving the error correction capability provided by the full parity check matrix

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11916667B1Cubic low-density parity-check code encoder
Publication Date: 2024.02.27 TARANA WIRELESS
  • US11916667B1 patent drawing
  • US11916667B1 patent drawing
  • US11916667B1 patent drawing

AI summary

Examples of check codes, methods of creating check codes, and communication systems utilizing check codes, such as low-density parity-check codes (LDPC codes) are described herein. In some examples, check codes described herein utilize a larger number of check operations than check bits.