CuCu Junction Wiring Structure With Low-k Insulation for RC Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with CuCu junctions face increased wiring delay due to the high relative dielectric constant of silicon oxide (SiO2) used in inter-wiring materials, which affects the RC delay and efficiency of wiring lines.
Innovation Solution
The use of low dielectric constant materials for all interlayer insulating layers in the multilayer wiring layer, with one surface of the wiring line facing a high dielectric constant insulating layer and the other surface in contact with a low dielectric constant insulating layer, reducing wiring delay while maintaining mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon oxide (SiO2) is used as inter-wiring materials in CuCu junction semiconductor devices, then mechanical strength is maintained, but wiring delay increases due to higher relative dielectric constant
Solution Approach 1:
The patent applies different dielectric materials to different locations within the wiring structure. Low-k materials are used specifically in interlayer insulating layers where wiring lines are formed, while SiO2 is used in other insulating layers. This local differentiation reduces RC delay in critical wiring regions while maintaining overall mechanical strength of the device.
Solution Approach 2:
The patent employs a composite insulating layer structure combining multiple materials with different properties. Low-k materials (with dielectric constant 3.0 or less) are combined with SiO2 layers in a multi-layer configuration, creating a composite structure that achieves both low wiring delay (through low-k regions) and sufficient mechanical strength (through SiO2 regions).
2Reliability
If low dielectric constant materials are used for all interlayer insulating layers, then wiring delay is reduced, but mechanical strength decreases and film peeling occurs
Solution Approach 1:
Low-k materials are selectively applied only to interlayer insulating layers that require low RC delay performance, while SiO2 is used in other insulating layers that primarily provide mechanical support and adhesion. This localized approach ensures wiring delay reduction without compromising overall film stability.
Solution Approach 2:
The patent creates a composite multi-layer insulating structure where low-k materials and SiO2 are combined. The SiO2 layers provide mechanical strength and prevent film peeling, while the low-k layers reduce dielectric constant and wiring delay. This composite approach balances electrical performance with mechanical stability.
Data Source
AI summary
A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.