CuCu Junction Wiring Structure With Low-k Insulation for Delay Reduction
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Solution Overview
Problem
Semiconductor devices with CuCu junctions experience significant wiring delay due to the use of silicon oxide (SiO2) as inter-wiring materials, which have a higher relative dielectric constant than Low-k materials, leading to increased RC delay.
Innovation Solution
The semiconductor device employs a multilayer wiring layer with interlayer insulating layers formed using Low-k materials, and the junction surfaces are reinforced with insulating layers having a lower dielectric constant to reduce wiring delay and maintain mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon oxide (SiO2) is used as inter-wiring material in CuCu junction semiconductor devices, then the device structure is simple and easy to manufacture, but the wiring delay increases due to higher relative dielectric constant
Solution Approach 1:
The patent changes the dielectric constant parameter of the insulating material from high (SiO2) to low (Low-k material with k<3.5), directly reducing the RC delay in wiring while maintaining the CuCu junction structure and manufacturing process
Solution Approach 2:
The patent uses composite material structures combining Low-k interlayer insulating layers with silicon oxide protective layers at junction surfaces, achieving both low wiring delay and high mechanical strength at the CuCu junction interface
2Loss of time
If Low-k materials are used for interlayer insulating layers to reduce wiring delay, then the wiring delay decreases, but the mechanical strength at junction surfaces may be reduced
Solution Approach 1:
The patent applies different material qualities to different locations: Low-k materials are used in interlayer insulating layers where low dielectric constant is needed, while silicon oxide materials with high mechanical strength are used at junction surfaces where structural strength is critical
Solution Approach 2:
The insulating structure is segmented into multiple functional layers: lower Low-k interlayer insulating layers for signal wiring delay reduction, and upper silicon oxide protective layers for junction surface mechanical strength and stability
Data Source
AI summary
A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.