CUDA Code Partitioning for CPU Execution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
CUDA applications designed for multi-core GPUs are not portable to general purpose CPUs without significant modifications, due to the lack of support for hundreds of hardware thread contexts and specific parallel execution features.
Innovation Solution
A method is developed to partition CUDA applications around synchronization barrier instructions, classify instructions as convergent or divergent, and replicate divergent memory references, inserting thread loops to ensure correct memory sharing, allowing the applications to run on general purpose CPUs without modification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CUDA applications are designed for multi-core GPUs with specific parallel execution features, then execution performance and parallel processing capability are improved, but portability to general purpose CPUs deteriorates
Solution Approach 1:
The CUDA application code is segmented into multiple partitions based on synchronization barrier instructions. Each partition contains a sequence of instructions that can be independently analyzed and transformed. This segmentation allows the translator to process different code regions with appropriate translation strategies, enabling portability to general purpose CPUs while preserving the original CUDA code structure and performance characteristics.
2Reliability
If the application program is partitioned around synchronization barrier instructions, then correct synchronization semantics are preserved, but code complexity increases
Solution Approach 1:
The translation process performs preliminary actions by analyzing and classifying instructions within each partition before generating the translated code. Instructions are classified as convergent or divergent, and necessary transformations (such as memory reference replication and thread loop insertion) are performed in advance. This preliminary processing ensures correct synchronization semantics are preserved while managing code complexity through systematic transformation rules.
3Reliability
If divergent memory references are replicated, then correct memory sharing between threads is ensured, but memory usage increases
Solution Approach 1:
The translation applies local quality by differentiating between convergent and divergent memory references. Only divergent memory references, which require replication to ensure correct thread-specific memory access, are copied. Convergent references are handled efficiently without unnecessary replication. This selective approach ensures memory sharing correctness while minimizing memory usage overhead.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.