Cumulative Integrity Check Value Processor for Memory Security
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Solution Overview
Problem
Current computer systems are vulnerable to memory attacks, such as cold boot attacks and data manipulation, due to the lack of effective encryption and integrity checking mechanisms, which can compromise processor architecture and steal sensitive data.
Innovation Solution
Implementing cumulative integrity check values (ICVs) using exclusive OR operations within the CPU's registers to provide encryption, integrity checking, and anti-replay protection without the performance degradation caused by version trees or excessive memory storage, allowing for the tracking of data integrity history.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If version trees or cryptographic hash trees are used for anti-replay checking, then memory integrity and anti-replay protection are improved, but memory latency increases significantly and throughput to main memory decreases
Solution Approach 1:
The patent extracts the integrity checking mechanism from complex version trees and simplifies it to cumulative ICVs stored directly in memory with each data write. This extraction removes the hierarchical structure overhead while maintaining integrity verification capability, thereby improving memory throughput without sacrificing reliability.
Solution Approach 2:
The patent changes the parameter of integrity verification from complex tree-based structures to simple cumulative ICV values that can be computed and verified with minimal overhead. This parameter change transforms the complexity from structural (tree nodes) to arithmetic (ICV computation), significantly reducing memory latency and improving throughput.
2Reliability
If cryptography circuits are implemented on the CPU to encrypt data before eviction to main memory, then data confidentiality is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the CPU's memory controller perform multiple functions: it not only manages memory allocation and access but also performs encryption and integrity verification of data before and after memory access. This multi-functionality eliminates the need for separate cryptography circuits, reducing device complexity while maintaining data confidentiality.
Solution Approach 2:
The CPU's memory controller serves itself by performing encryption and integrity checking operations that would otherwise require separate dedicated hardware circuits. This self-service approach reduces overall device complexity while maintaining strong security guarantees for data confidentiality and integrity.
3Reliability
If ICV values are stored inside the CPU package for each cacheline, then anti-replay protection is improved, but excessive CPU memory is required and multiple read/writes are needed for every data access
Solution Approach 1:
The patent moves the ICV storage from the CPU package dimension to the main memory dimension. Instead of storing ICVs in CPU-internal structures that consume valuable CPU memory resources, the ICVs are stored alongside data in main memory. This dimensional change eliminates the constraint on CPU memory quantity while maintaining anti-replay protection.
Solution Approach 2:
The patent merges the data storage and ICV storage into a single memory location. The ICV is stored together with the corresponding data in main memory, eliminating the need for separate ICV storage structures. This merging reduces the total quantity of memory resources required while maintaining integrity verification capability.
Data Source
AI summary
In general, in one aspect, the disclosure describes a process that includes a cryptographic engine and first and second registers. The cryptographic engine is to encrypt data to be written to memory, to decrypt data read from memory, to generate read integrity check values (ICVs) and write ICVs for memory accesses. The cryptographic engine is also to create a cumulative read ICV and a cumulative write ICV by XORing the generated read ICV and the generated write ICV with a current read MAC and a current write ICV respectively and to validate data integrity by comparing the cumulative read ICV and the cumulative write ICV. The first and second registers are to store the cumulative read and write ICVs respectively at the processor. Other embodiments are described and claimed.