3D Cup Capacitor Structure for High Capacitance in Less Chip Area
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Solution Overview
Problem
MIM capacitors struggle to scale in size with decreasing minimum feature sizes of integrated chips, leading to increased area consumption and costs while maintaining capacitance.
Innovation Solution
A capacitor structure with a double-layered capacitor dielectric structure and electrically connected upper electrodes, allowing for a compact design that achieves high capacitance with reduced substrate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MIM capacitors are used in traditional metal layers, then they can serve different functional circuits, but they consume increased substrate area as minimum feature sizes decrease
Solution Approach 1:
The patent transitions capacitor fabrication from traditional planar metal layers to a vertical three-dimensional structure using deep trench capacitors. This dimensional change allows capacitors to be formed in the depth direction rather than consuming horizontal substrate area, enabling high capacitance values while maintaining small footprints on the chip surface.
Solution Approach 2:
The patent implements a nested structure where the capacitor dielectric material is positioned within the deep trench, surrounded by conductive materials that form the capacitor electrodes. This nested arrangement maximizes the use of vertical space within the trench structure, increasing capacitance density without expanding the horizontal area occupied by each capacitor.
2Productivity
If capacitor size is reduced to match decreasing feature sizes, then integration density improves, but capacitance value decreases
Solution Approach 1:
The patent changes the geometric parameters of the capacitor structure by forming deep trenches with significant depth-to-width ratios. This parameter change allows the capacitor active area to extend vertically rather than horizontally, maintaining or increasing capacitance values while reducing the horizontal footprint to match scaled-down feature sizes and improve integration density.
Solution Approach 2:
The patent employs composite material structures combining different dielectric materials with varying dielectric constants in the capacitor structure. By stacking dielectric layers with different properties, the patent achieves higher effective capacitance in the vertical direction, compensating for the reduced horizontal dimensions and enabling high capacitance in a compact form factor.
Data Source
AI summary
A memory device having a capacitor structure and a method of forming the same are provided. The memory device includes a substrate; a dielectric layer disposed on the substrate; and a plurality of capacitor structures respectively disposed in the dielectric layer. Each capacitor structure includes: a cup-shaped lower electrode; a first upper electrode conformally covering an outer surface of the cup-shaped lower electrode; a first capacitor dielectric layer disposed between the outer surface of the cup-shaped lower electrode and the first upper electrode; a second upper electrode conformally covering an inner surface of the cup-shaped lower electrode, wherein the second upper electrode is electrically connected to the first upper electrode by at least one connection via; and a second capacitor dielectric layer disposed between the inner surface of the cup-shaped lower electrode and the second upper electrode.