Cup-Shaped DRAM Capacitor Electrode With TiN/SiN Etch Control

The patent applies local quality by creating a cup-shaped bottom electrode geometry with enhanced sidewall contact area, and by using alternating TiN/SiN layers with different etch resistance properties in specific regions. The SiN layers provide higher etch resistance at the sidewalls to maintain contact area, while TiN layers provide conductivity. This localized differentiation of material properties and geometric features addresses the leakage issue without requiring overall capacitor size increase.

The patent employs composite materials by stacking alternating layers of titanium nitride (TiN) and silicon nitride (SiN) to form the bottom electrode. TiN provides electrical conductivity while SiN provides higher etch resistance. This composite structure maintains low leakage current by preserving the electrode-dielectric contact area during etching processes, even as capacitor dimensions are reduced.

The patent segments the bottom electrode into alternating thin layers of TiN and SiN, with each layer serving a specific function. The TiN layers provide conductivity while SiN layers provide etch resistance. This segmentation allows the complex performance requirements (low leakage, good conductivity, etch resistance) to be met through layered composition rather than a single complex structure.

The patent changes material parameters by selecting TiN and SiN with complementary properties - TiN for conductivity and SiN for etch resistance. The layer thicknesses are optimized (total TiN thickness greater than total SiN thickness) to balance electrical performance with etch resistance. These parameter optimizations reduce leakage current while keeping the fabrication process compatible with existing CMOS technology.