Circuit-Under-Pad GaN Transistors for High Current Density
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Solution Overview
Problem
Existing Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors face limitations in current carrying capability, on-chip parasitic capacitances, and inductances, which hinder their application in high current power switching systems.
Innovation Solution
The proposed CUP device topologies feature a semiconductor structure with a lateral GaN transistor comprising active regions with optimized on-chip metallization, including a drain pad and split source pads, interconnected by conductive micro-vias, which reduces resistance, capacitances, and inductances, and enhances current density across the active region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional non-CUP device topologies are used with peripheral contact pads, then external connections are provided, but the metal interconnect buses and contact pads occupy significant inactive area around the periphery of the chip, limiting the usable fraction of die area for active device regions
Solution Approach 1:
The patent transitions from traditional peripheral contact pads in the lateral dimension to vertical CUP structures where contact pads are positioned above active device regions in the vertical dimension. This dimensional change allows contact pads to be stacked over active regions rather than occupying peripheral space, thereby increasing the usable die area for active devices while maintaining external connection functionality.
Solution Approach 2:
The patent implements a nested structure where contact pads are positioned vertically above active device regions, with intermediate conductive layers and vias connecting different levels. This nesting approach allows multiple functional layers to occupy the same lateral footprint, effectively increasing the usable die area without expanding the chip perimeter.
2Quantity of substance
If known CUP device topologies are implemented for high current power switching devices, then die area utilization is improved, but current carrying capability remains limited
Solution Approach 1:
The patent divides the contact pad structure into multiple segments including drain contact pads, source contact pads, and intermediate conductive layers with vias. This segmentation allows current to flow through multiple parallel paths, increasing the overall current carrying capability while distributing the electrical load across different structural elements of the CUP topology.
Solution Approach 2:
The patent employs composite interconnect structures combining multiple metal layers, conductive vias, and dielectric materials to enhance current carrying capability. The multi-layer composite structure provides both mechanical support and optimized electrical performance for high current power switching applications.
3Object-affected harmful factors
If known CUP device topologies are used, then die area utilization is increased, but on-chip parasitic capacitances and inductances are not sufficiently reduced
Solution Approach 1:
The patent optimizes the local electrical characteristics of the CUP structure by positioning drain contact pads and source contact pads with specific geometries and spacing. The intermediate conductive layers and via structures are designed with localized properties to minimize parasitic capacitances between adjacent pads and reduce gate loop inductances, thereby reducing harmful parasitic effects while maintaining high die area utilization.
4Power
If large area lateral GaN transistors are designed for high voltage/high current operation, then power switching capability is enhanced, but gate drive phase equalization and current balance become more difficult
Solution Approach 1:
The patent uses vertical CUP structures to provide distributed gate drive connections to multiple active device regions. The intermediate conductive layers and vias create symmetrical current paths that equalize gate drive phases across large area transistors, making high power operation more controllable while maintaining scalability.
Data Source
AI summary
Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.