Cup-Shaped Memory Capacitor Structure for High Capacitance Density
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Solution Overview
Problem
MIM capacitors struggle to scale in size with decreasing minimum feature sizes of integrated chips, leading to increased area consumption and costs while maintaining capacitance.
Innovation Solution
A capacitor structure with a double-layered capacitor dielectric structure and electrically connected upper electrodes, allowing for a smaller footprint while maintaining high capacitance and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional MIM capacitors are used in integrated chips, then capacitance function is achieved, but area consumption increases as minimum feature sizes decrease
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional vertically stacked capacitor structures. Multiple capacitor units are stacked in the vertical direction, allowing capacitance to be increased without proportionally increasing the horizontal footprint. This dimensional change enables the capacitor to maintain required capacitance values while occupying less chip area as feature sizes scale down.
Solution Approach 2:
The patent implements nested capacitor structures where conductive plates and dielectric layers are arranged in concentric or stacked configurations. Inner conductive elements are surrounded by outer conductive elements with dielectric materials in between, creating a nested arrangement that maximizes capacitance density within a compact volume, thereby reducing the area required per unit capacitance.
2Area of stationary object
If capacitor size is reduced to maintain integration density, then chip area decreases, but capacitance value may be compromised
Solution Approach 1:
By stacking multiple capacitor units vertically, the patent increases the effective capacitance volume without increasing the horizontal chip area. The vertical stacking allows multiple capacitance-contributing layers to be combined within the same footprint, maintaining total capacitance while reducing the area each capacitor occupies.
Solution Approach 2:
The patent employs composite structures combining multiple dielectric materials and conductive layers in a stacked configuration. Different dielectric layers with varying permittivity values are combined to optimize the overall capacitance density, enabling high capacitance values in a compact form factor that reduces chip area consumption.
3Object-generated harmful factors
If traditional single-layer capacitor structures are used, then manufacturing is simpler, but parasitic capacitance is higher
Solution Approach 1:
The patent divides the capacitor into multiple segmented units stacked vertically, with each unit having its own conductive plates and dielectric layers. This segmentation allows for better isolation of electrical signals and reduces unwanted coupling between adjacent conductive elements, thereby lowering parasitic capacitance effects while managing the increased structural complexity through modular design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables a memory device with high charge capacity and low parasitic capacitance, enhancing storage density and performance while minimizing chip area and cost.
Implementation Method 1
Metal-Insulator-Metal (MIM) capacitors have been widely used in functional circuits
Implementation Method 2
a first capacitor dielectric layer and a second capacitor dielectric layer
Data Source
AI summary
A memory device having a capacitor structure and a method of forming the same are provided. The memory device includes a substrate; a dielectric layer disposed on the substrate; and a plurality of capacitor structures respectively disposed in the dielectric layer. Each capacitor structure includes: a cup-shaped lower electrode; a first upper electrode conformally covering an outer surface of the cup-shaped lower electrode; a first capacitor dielectric layer disposed between the outer surface of the cup-shaped lower electrode and the first upper electrode; a second upper electrode conformally covering an inner surface of the cup-shaped lower electrode, wherein the second upper electrode is electrically connected to the first upper electrode by at least one connection via; and a second capacitor dielectric layer disposed between the inner surface of the cup-shaped lower electrode and the second upper electrode.