Current-Mode ADC With DAC Feedback for Low-Power Current Sensing
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Solution Overview
Problem
Prior art analog to digital converters (ADCs) are highly consumptive of power and provide relatively low resolution, making them unsuitable for applications with limited power budgets and requiring high performance.
Innovation Solution
The development of novel ADC designs and architectures that enable high-resolution digital format data conversion with simultaneous drive and sense capabilities, utilizing a single line for both driving and sensing analog signals, and incorporating non-linear N-bit digital to analog converters (DACs) for efficient power management and broad dynamic range sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prior art ADC designs are used, then device complexity is reduced, but power consumption increases significantly and resolution decreases
Solution Approach 1:
The patent combines drive and sense operations into a single shared line, eliminating the need for separate dedicated lines. This merging reduces device complexity while enabling more efficient power management and higher resolution measurements through the integrated architecture.
Solution Approach 2:
The shared line serves multiple functions: it acts as both a drive line for delivering signals and a sense line for receiving feedback. This multi-functionality reduces the overall number of components and simplifies the device structure while maintaining high resolution and low power consumption.
2Measurement precision
If prior art ADC designs are used, then device complexity is reduced, but measurement precision decreases
Solution Approach 1:
The patent combines drive and sense operations into a single shared line, eliminating the need for separate dedicated lines. This merging reduces device complexity while enabling more efficient power management and higher resolution measurements through the integrated architecture.
3Use of energy by moving object
If prior art ADC designs are used, then ease of operation is maintained, but power consumption increases
Solution Approach 1:
The patent incorporates feedback mechanisms that monitor and adjust power consumption dynamically. The system automatically optimizes its operation based on measured conditions, maintaining ease of use while significantly reducing power consumption through intelligent control.
4Use of energy by moving object
If non-linear N-bit DACs are incorporated, then power consumption is reduced and dynamic range is expanded, but device complexity increases
Solution Approach 1:
The patent employs non-linear N-bit DACs that utilize parameter changes in the digital domain to achieve more efficient analog output. By transforming the digital signal through non-linear parameters before conversion, the system reduces power consumption and expands dynamic range while managing complexity through mathematical transformations.
Data Source
AI summary
An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).