Current-Mode ADC Thermometer Coding for Mismatch Linearity
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Solution Overview
Problem
Analog to digital converters (ADCs), particularly current mode ADCs, face challenges in precision due to normal and random mismatch of field effect transistors (FETs) in CMOS manufacturing, leading to increased manufacturing costs and reduced accuracy at low voltage power supplies and low currents, which restricts input range and signal-to-noise ratio.
Innovation Solution
A signal conditioning method that involves cascading signal conditioning blocks to generate thermometer codes, utilizing current mirrors and steering circuits to compare input currents with reference currents, and producing digital output signals that are polarity-dependent, effectively reducing the impact of FET mismatch and enabling operation at low voltage and low current conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ADCs rely on FET matching for accuracy in standard CMOS manufacturing, then manufacturing costs are reduced, but precision and resolution decrease due to normal and random mismatch
Solution Approach 1:
The patent replaces voltage-mode operation with current-mode operation. Current-mode ADCs use current mirrors and current steering circuits instead of voltage switching, which reduces sensitivity to FET mismatch while maintaining ease of CMOS manufacturing. The current mirrors inherently compensate for process variations, achieving both low cost and high precision.
Solution Approach 2:
The patent changes the operating parameters by using current signals instead of voltage signals throughout the conversion process. This parameter change from voltage to current domain operation fundamentally alters the sensitivity characteristics, making the system less sensitive to FET mismatch and enabling high precision without expensive trimming or calibration.
2Use of energy by moving object
If ADCs operate at low voltage power supplies, then power consumption is reduced, but input range and signal-to-noise ratio are restricted
Solution Approach 1:
The patent uses current-mode circuitry throughout, including current mirrors and current steering circuits. Current-mode operation allows for better noise performance and wider effective input range at low voltages compared to voltage-mode operation, as current signals are less susceptible to voltage noise and can maintain signal integrity with smaller voltage swings.
3Use of energy by moving object
If ADCs operate at low currents, then power consumption is reduced, but conversion speed decreases
Solution Approach 1:
The patent employs current-mode logic and current steering circuits that offer faster switching speeds compared to voltage-mode switching. Current-mode operation reduces the time constants associated with charging and discharging capacitances, enabling faster conversion rates even at low current levels. The current mirrors provide rapid response to input changes, maintaining high speed performance.
4Measurement precision
If sampling ADCs utilize switching techniques such as switch capacitors, then high accuracy is achieved, but dynamic power consumption increases due to free running clock requirement
Solution Approach 1:
The patent employs a periodic clocking scheme for the current steering circuits, where the clock signal controls the timing of current switching. This periodic action enables accurate conversion while allowing the circuit to remain in a low-power state between clock cycles, significantly reducing dynamic power consumption compared to continuous free-running switching architectures.
Data Source
AI summary
A family of current mode analog to digital converters, or TiADC, utilizing methods, circuits, and apparatuses, are disclosed with the following benefits: (1) There are normal and random non-systematic mismatch between devices in silicon manufacturing, that introduce non-linearity in current mode analog to digital converter's, or iADC, reference network. The iADC's linearity is improved by utilizing a thermometer current mode signal conditioning method, SCM. Successive applications of the SCM effectuates a segmented current reference network to function like a thermometer network, which operates based on the function of summation. Having a TiADC with a thermometer reference network, where current segments are summed or accumulated incrementally, would inherently reduce the impact of statistical distribution of component's random mismatch on the iADC's non-linearity. Accordingly, linearity of TiADC can be improved by the square root of the sum of the square of mismatch errors of the number of segmented current references in the thermometer network. (2) speed is improved by operating the TiADC in current mode, which is inherently faster. (3) voltage swings in current mode are small, which enables the iADC to operate at lower power supply voltages. (4) The TiADC can operate in subthreshold and at very low currents, which lower powers consumption. (5) the TiADC is asynchronous. Being clock free, TiADC has lower dynamic power consumption with reduces digital system noise. (6) the signal conditioning method or SCM utilized in TiADC provides concurrent functions of analog differencing and digital comparison. This trait enhances the dynamic response of iADC, wherein the digital output throughput accuracy degrades gradually and not abruptly as a function of increasing frequency of iADC's input signal. (7) No passive devices, such as capacitors or resistors, are required for the TiADC. (8) TiADC can be fabricated on low cost mainstream standard digital CMOS processes.