Current Aperture Transistor Hybrid Layer Breakdown Voltage
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Solution Overview
Problem
Conventional transistors often experience breakdown voltage limitations due to field crowding at the gate trench corners, which restricts their high voltage/high power applications, and current aperture transistors aim to achieve near bulk breakdown limits in nitride-based devices but require further enhancements.
Innovation Solution
The development of current aperture transistors with a hybrid layer of semiconductor material, including regions of p-type, insulating, and n-type nitride-based materials, where a pendeo-epitaxial layer with higher doping levels is laterally grown to form a current aperture that allows for a two-dimensional electron gas (2DEG) formation, enabling vertical and horizontal channel regions and improved charge modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor structures are used, then manufacturing is simpler, but breakdown voltage is limited due to field crowding at gate trench corners
Solution Approach 1:
The transistor structure is segmented into multiple functional regions including a drift region, a current aperture region with insulating material, and a gate region. This segmentation allows the high field region to be buried in the bulk material rather than concentrated at the gate trench corners, enabling breakdown voltages that approach the bulk breakdown limit of the semiconductor material.
Solution Approach 2:
An insulating material is introduced as an intermediary element within the current aperture region. This insulating material modifies the electric field distribution by preventing field crowding at the gate trench corners, thereby enabling the device to sustain higher breakdown voltages without requiring complete structural redesign.
2Reliability
If current aperture transistors are designed to achieve near bulk breakdown limits, then breakdown voltage improves, but charge accumulation occurs at the gate edge
Solution Approach 1:
The harmful charge accumulation at the gate edge is extracted or eliminated by designing the current aperture region with insulating material that prevents charge buildup. The insulating material acts as a barrier that stops charge carriers from accumulating at the gate trench corners, thereby removing the harmful effect while maintaining the high breakdown voltage capability.
3Reliability
If the high field region is buried in bulk material, then breakdown voltage increases, but device structure becomes more complex
Solution Approach 1:
The device structure implements local quality by concentrating the insulating material specifically in the current aperture region where it is most needed to prevent field crowding. This localized approach achieves the desired high breakdown voltage without requiring complex modifications throughout the entire device structure, thereby balancing performance improvement with structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the breakdown voltage characteristics by burying the high field region in the bulk material, reducing charge accumulation at the gate edge and increasing the transistor's potential applications in high voltage/high power electronics.
Implementation Method 1
a pendeo-epitaxial layer with higher doping levels is laterally grown to form a current aperture
Implementation Method 2
configured to provide a two-dimensional electron gas (2DEG) in a region of an interface between the first and second semiconductor material layers
Data Source
AI summary
Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.