Current-Based BIST for Varied-Configuration Circuit Defect Detection
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Solution Overview
Problem
Conventional testing methods for semiconductor circuits, particularly analog circuits, are inefficient and costly due to the reliance on external equipment, which is large, expensive, and slow, leading to challenges in achieving thorough test coverage and high reliability, especially in high-stakes applications.
Innovation Solution
Implementing current-based built-in self-testing (BIST) techniques that rearrange circuit components into varied configurations to measure and compare currents, detecting defects based on discrepancies in current draw, thereby reducing reliance on external testing equipment and enhancing test coverage and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external testing equipment is used to test semiconductor circuits, then test coverage can be achieved, but the testing process becomes slow and costly
Solution Approach 1:
The patent implements built-in self-testing (BIST) where the circuit under test generates its own test patterns and evaluates its own functionality. Test logic is integrated within the circuit, allowing it to autonomously perform testing without external equipment, thereby achieving both thorough test coverage and high testing speed
Solution Approach 2:
The patent merges the test pattern generator, test stimulus source, and response evaluator into the circuit itself. By combining these previously separate external testing functions into integrated on-chip test logic, the system achieves both comprehensive testing capability and rapid testing throughput
2Reliability
If external testing equipment is used to test semiconductor circuits, then test coverage can be achieved, but the cost increases significantly
Solution Approach 1:
By implementing self-testing capability within the circuit, the patent eliminates the need for expensive external testing equipment. The integrated BIST logic performs comprehensive testing using on-chip resources, significantly reducing manufacturing costs while maintaining high test coverage
Solution Approach 2:
The patent uses simple, low-cost on-chip test logic and standard circuit components to perform comprehensive testing, replacing expensive external testing equipment with affordable integrated test structures that can be manufactured at minimal additional cost
3Reliability
If external testing equipment is used to test semiconductor circuits, then thorough testing can be performed, but the equipment size and complexity increase
Solution Approach 1:
The patent integrates test pattern generation, stimulus application, and response evaluation logic directly within the circuit under test. This self-service approach performs thorough testing using only on-chip resources, eliminating complex external testing equipment and reducing overall system complexity
Solution Approach 2:
The patent nests the test logic within the operational circuit structure itself. The BIST functionality is embedded as integrated logic within the existing circuit blocks, allowing thorough testing to be performed without adding external testing equipment or increasing system complexity
4Ease of operation
If circuit components are tested in fixed configurations, then testing is simple, but defect detection capability is limited
Solution Approach 1:
The patent dynamically reconfigures circuit components between different operational configurations and test configurations using controllable switches. This dynamic reconfiguration allows the same physical components to serve multiple functions - normal operation and various testing modes - maintaining simplicity while enhancing defect detection capability
Solution Approach 2:
The patent changes the operational parameters of circuit components by reconfiguring switch states to alter circuit topology. By changing parameters such as component connectivity and signal flow paths through controlled reconfiguration, the system achieves both ease of operation and comprehensive defect detection
Data Source
AI summary
A self-testing circuit may transmit a first test vector to a test block of a plurality of test blocks in the self-testing circuit. The first test vector may correspond to a first configuration for a set of components in the test block. The self-testing circuit may measure a first current drawn by the test block when the set of components is in the first configuration. The self-testing circuit may also transmit a second test vector to the test block, the second test vector corresponding to a second configuration for the set of components. The self-testing circuit may measure a second current drawn by the test block when the set of components is in the second configuration. Based on a comparison between the first and second currents, the self-testing circuit may detect a defect in the test block.