Current-Boosted Level Shifter for Faster Cross-Voltage Switching

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Solution Overview

Problem

Voltage level shifters experience imbalances in current flow due to discrepancies in conductivity states of transistors, leading to delays and slow switching, particularly when different supply voltages are involved.

Innovation Solution

Incorporation of current boosting stages that provide selective current paths to balance current flow during state transitions, regardless of the relationship between the first and second supply voltages, using transistors driven by higher or lower voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If transistors of the same size are used in the level shifter, then device complexity is reduced, but current flow becomes imbalanced causing switching delays

Engineering Contradiction:
Improvetransistor size variationVSAvoidswitching delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent introduces current boosting stages as intermediary components between the input and output stages. These stages include transistors (e.g., MP10, MN10, MP11, MN11) that are selectively activated to provide additional current paths, mediating the current flow imbalance caused by using uniformly sized transistors throughout the level shifter.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the operational parameters of specific transistors by activating them in different states depending on the voltage domain relationship. When the first voltage domain is higher than the second, certain transistors are activated to boost current; when the first voltage domain is lower, different transistors are activated. This dynamic parameter change balances current flow without requiring all transistors to be differently sized.

Inventive Principle:
Principle #35Parameter changes

2Speed

If current boosting stages are added to balance current flow, then switching speed is improved, but device complexity increases

Engineering Contradiction:
Improveswitching speedVSAvoidcircuit structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The current boosting stages are designed to serve multiple functions: they balance current flow during high-to-low voltage transitions, balance current flow during low-to-high voltage transitions, and can be selectively activated based on operating conditions. The same structural framework handles different voltage domain relationships, reducing the need for entirely separate circuits for each scenario.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The current boosting stages are dynamically activated and deactivated based on the relationship between the first and second voltage domains. Control logic selectively enables specific transistors in the boosting stages only when needed, allowing the circuit to adapt its complexity to the operating conditions rather than maintaining fixed high complexity in all states.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12537527B2Level shifter having current boosting stages
Publication Date: 2026.01.27 STMICROELECTRONICS INT NV
  • US12537527B2 patent drawing
  • US12537527B2 patent drawing
  • US12537527B2 patent drawing

AI summary

A level shifter having current boosting stages is provided. The level shifter includes a level shifting stage including a plurality of transistors and first and second nodes. The level shifting stage is configured to transfer a first signal of a first voltage domain to a second signal of a second voltage domain. A plurality of current boosting stages are associated with the transistors, respectively. A first current boosting stage provides a first boosting stage current path to support a first level shifter current path of a first transistor of the plurality of transistors in response to: a first supply voltage of the first voltage domain being greater than a second supply voltage of the second voltage domain, the first signal having a first logical state and the first node having a logical state reflecting that the first signal has a second logical state different from the first logical state.