Current-Cell DAC Calibration Without AC Path Capacitance Penalty

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Solution Overview

Problem

Conventional digital-to-analog converters with current source cells in a matrix configuration face issues with alternating current characteristics due to parasitic capacitance and process variations, which are not effectively addressed by existing calibration methods.

Innovation Solution

The digital-to-analog converter employs a cascode connection of current source transistors during regular operation and uses a calibration transistor in place of one current source transistor during calibration, avoiding parasitic capacitance at the current source switch node and allowing for correction of current values, while sharing a single current corrector across multiple cells to reduce circuit size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a calibration switch is added to each current source cell for calibration operation, then calibration capability is improved, but parasitic capacitance at the current source switch node increases, deteriorating alternating current characteristics

Engineering Contradiction:
Improvecalibration capabilityVSAvoidparasitic capacitance
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The calibration switch is extracted from the current source switch node and placed separately, so that when the calibration switch is turned on during calibration, it does not add parasitic capacitance to the current source switch node. This separation allows calibration functionality without degrading AC characteristics.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The calibration path is segmented from the main current source path. The calibration switch operates in a separate calibration mode, allowing the calibration function to be independent from the signal path, thereby avoiding parasitic capacitance interference with alternating current characteristics.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple current source transistors are used in each current source cell, then current source functionality is improved, but circuit complexity increases

Engineering Contradiction:
Improvecurrent source functionalityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The circuit configuration is made dynamic by using a control signal to switch between different transistor connections. During calibration mode, transistors are connected in a first configuration, and during normal operation, they are connected in a second configuration, allowing the same hardware to serve multiple functions without permanent complexity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The current source transistors serve multiple functions: they act as current sources during normal operation and as calibration elements during calibration mode. This multi-functionality reduces the need for separate dedicated calibration transistors, thereby reducing overall circuit complexity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7683813B2Digital-to-analog converter carrying out calibration operation for current source cells
Publication Date: 2010.03.23 LAPIS SEMICON CO LTD
  • US7683813B2 patent drawing
  • US7683813B2 patent drawing
  • US7683813B2 patent drawing

AI summary

A current cell matrix type of digital-to-analog (D/A) converter to prevent deterioration of a.c. characteristics on a current path for digital-to-analog conversion includes a array of current source cells arranged in a matrix configuration. Each current source cell includes a current source transistor to generate the cell current. During the regular operation, the cell current is flowed on output lines via a first transistor connected in cascode to the current source transistor. During the calibration operation, the cell current is flowed into a current comparator via a second transistor connected in cascode to the current source transistor. This prevents parasitic capacitance from being additively caused in switches for the first transistor and in another switch for the second transistor to prevent deterioration of a.c. characteristics on the current path.