Common-Gate Current Comparator for Low-Capacitance Fast Switching
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Solution Overview
Problem
Current comparators face challenges in achieving fast operational speed due to high input impedance and input capacitance, which limit bandwidth and increase propagation delay.
Innovation Solution
The proposed current comparator design incorporates a P-type metal oxide semiconductor field effect transistor (PMOS FET) and an N-type metal oxide semiconductor field effect transistor (NMOS FET) in a common gate configuration, with a bias circuit providing bias voltages to maintain the transistors in the saturation region. This design decouples the input from external capacitances, reducing effective input capacitance and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional current comparator design is used, then input impedance is high, but operational speed is slow due to high input capacitance and bandwidth limitations
Solution Approach 1:
The input stage is segmented into two separate gates (first gate and second gate) that are independently biased. This segmentation allows each gate to be optimized for specific functions, reducing the overall input capacitance while maintaining high input impedance through the differential configuration.
Solution Approach 2:
The biasing parameters are changed by applying different bias voltages to the first and second gates independently. This parameter change enables the transistors to operate in optimal regions, reducing input capacitance effects and improving operational speed without sacrificing input impedance.
2Speed
If bias voltages are applied to maintain transistors in saturation region, then operational speed improves, but power consumption increases
Solution Approach 1:
The bias circuit applies bias voltages only when needed to maintain transistor saturation during critical switching operations. The bias is dynamically adjusted to provide just enough overdrive to keep transistors in saturation during high-speed operation, rather than continuously maximizing the bias, thus reducing unnecessary power consumption.
3Area of stationary object
If minimum size transistors are used, then area is reduced, but resolution is lost
Solution Approach 1:
The first and second transistors are designed with asymmetric characteristics - they have different threshold voltages and transconductance parameters. This asymmetry is intentionally introduced through different biasing of the first and second gates, allowing minimum-size transistors to achieve better resolution by exploiting the differential effect of asymmetric device characteristics rather than relying on large device sizes.
Data Source
Figure 1~2a
Figure 2b~2c
Figure 3~4a
AI summary
A current comparator comprising: a P-type metal oxide semiconductor field effect transistor, PMOS FET (614), and an N-type metal oxide semiconductor field effect transistor, NMOS FET (615). The source of the PMOS FET is connected to a first comparator input terminal (610). The source of the NMOS FET is connected to a second comparator input terminal (611). The drain of the PMOS FET is connected to a current-comparator-input-node (602). The drain of the NMOS FET is connected to the current-comparator-input-node. The gate of the PMOS FET is connected to a first bias-voltage-node (VP). The gate of the NMOS FET is connected to a second bias-voltage-node (VN). The current comparator also includes a bias circuit (613) that provides a bias voltage to each of the first and second bias-voltage-nodes, and a current-comparator-circuit (601). A current-comparator-circuit-input-terminal (602) is connected to the current-comparator-input-node in order to receive a difference-current-input signal (IIn), which is representative of the difference between a first current input signal and a second current input signal. The current-comparator-circuit is configured to provide a current comparator output signal (Vout) as a digital voltage signal based on the received difference-current-input signal.