Current Comparison Readout Circuit for Low-Power Flash Memory
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Solution Overview
Problem
The increasing demand for high data bit width and low power consumption in non-volatile eflash memories poses a challenge for optimizing read operation power consumption, particularly due to high parasitic loads and frequent address changes in column decoders.
Innovation Solution
A semiconductor memory design with paired memory arrays and decoders, where one array is enabled while the other is disabled, reducing parasitic loads by matching BLs to ports in the comparison readout circuit, and optimizing switch signal changes to minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If column decoders frequently change address signals during read operations, then memory access flexibility is improved, but power consumption increases due to frequent switch signal changes
Solution Approach 1:
The patent implements dynamic control of column decoders where only one decoder is activated at a time based on memory array selection. The decoders switch between enabled and disabled states dynamically, reducing unnecessary signal transitions and power consumption while maintaining flexible memory access capability through selective activation.
Solution Approach 2:
The system employs periodic alternating activation of paired column decoders corresponding to different memory arrays. When one array is selected, its decoder is enabled while the other is disabled, creating a periodic on-off pattern that reduces overall power consumption compared to continuous operation of all decoders.
2Reliability
If paired memory arrays with paired column decoders are used, then readout reliability is improved through current comparison, but device complexity increases
Solution Approach 1:
The patent merges the functionality of two separate readout paths into a single comparison readout circuit. By combining the current outputs from selected memory cells through the bitline and comparing them simultaneously in one circuit, the system achieves reliable differential readout while avoiding the complexity of completely independent readout circuits for each array.
Solution Approach 2:
The comparison readout circuit serves multiple functions: it reads data from either memory array, performs differential comparison, and provides reliable readout output. This multi-functional design reduces overall system complexity by using a single versatile circuit rather than separate specialized circuits for each function.
3Loss of energy
If bitlines are coupled to comparison readout circuit ports, then parasitic loads are reduced through matching, but device complexity increases due to additional coupling configurations
Solution Approach 1:
The coupling between bitlines and comparison readout circuit ports is dynamically configured based on which memory array is active. The system adaptively connects the appropriate bitline to the comparison circuit, optimizing parasitic load matching in real-time without requiring complex static wiring configurations for all possible connections.
Data Source
AI summary
A semiconductor memory comprising: a comparison readout circuit comprising a first port configured to receive an electric signal of a read memory unit and a second port configured to receive a reference electric signal, the comparison readout circuit being configured to compare the electric signal of the read memory unit with the reference electric signal to obtain storage information of the memory unit; and a first/second column decoder connected to a first/second memory array and the comparison readout circuit and configured to select a bitline corresponding to the read memory unit when a memory array selection signal enables the first/second memory array, and output the electric signal of the memory unit to the first port by means of the bitline, and further configured to connect a first bitline of the first/second memory array to the second port when the memory array selection signal does not enable the first/second memory array.