Current-Controlled Delay Circuit for High-Frequency Signal Tuning

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Solution Overview

Problem

Existing clock and data recovery (CDR) technologies face limitations due to high parasitic capacitive loads caused by varactors, which reduce the maximum achievable frequency of voltage-controlled ring oscillators and increase parasitic capacitance, hindering efficient signal processing.

Innovation Solution

A device comprising multiple differential pairs and adjustable quiescent current sources with current modulation stages is used to control the delay of electrical signals, reducing parasitic loads by varying the quiescent current settings, thereby enhancing frequency modulation without adding capacitive elements to the signal path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If varactors are used to adjust oscillation frequency in voltage-controlled ring oscillators, then frequency tuning capability is improved, but parasitic capacitive load increases and maximum achievable frequency decreases

Engineering Contradiction:
Improvefrequency tuning capabilityVSAvoidparasitic capacitive load
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and removes the varactor elements from the oscillator circuit. Instead of using varactors for frequency tuning, the invention employs a delay element with controllable delay time that is coupled to the oscillation circuit. This separation eliminates the parasitic capacitance problem inherent in varactor-based tuning while preserving frequency adjustment capability through digital control of the delay element.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the analog varactor-based continuous frequency tuning mechanism with a digital delay control mechanism. The delay element's delay time is controlled by digital signals from a phase detector and frequency control unit, substituting the analog capacitor adjustment approach with a digital timing control approach that avoids parasitic capacitance issues.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If multiple varactors are used to achieve frequency control, then frequency adjustment range is improved, but device complexity and parasitic capacitance increase

Engineering Contradiction:
Improvefrequency adjustment rangeVSAvoidnumber of varactor components
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent makes the delay element serve multiple functions: it provides both the timing function for oscillation and the frequency tuning function. By controlling the delay time of this single element, the oscillator frequency can be adjusted across a wide range. This multi-functionality eliminates the need for multiple separate varactor components, reducing device complexity while maintaining broad frequency adjustment capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If varactors are inserted into the signal path for frequency control, then frequency modulation capability is improved, but signal quality deteriorates due to increased parasitic capacitance

Engineering Contradiction:
Improvefrequency modulation capabilityVSAvoidsignal quality
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a delay element as an intermediary component between the control signals and the oscillation circuit. This delay element acts as a mediator that translates delay time adjustments into frequency modulation without directly inserting capacitive elements into the signal path. The intermediary delay element preserves signal quality while enabling frequency modulation capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10951217B2Device and method for controllably delaying electrical signals
Publication Date: 2021.03.16 SILICON LINE
  • US10951217B2 patent drawing
  • US10951217B2 patent drawing

AI summary

A device and method for controllably delaying an electrical signal includes a first signal transfer path between a signal input and a signal output. The first signal transfer path includes a first signal transfer stage with a first differential pair and a common, adjustable first quiescent current source, and a second signal transfer path between the signal input and the signal output. The second signal transfer path includes a second signal transfer stage with a second differential pair and a common, adjustable second quiescent current source. An internal delay stage is arranged between the signal input and the second signal transfer stage and has a third differential pair and a common, adjustable third quiescent current source, and signal combination stage for additively superimposing the electrical signal transferred via the first signal transfer path on to the electrical signal transferred via the second signal transfer path.