Current DAC Row-Decoding Scheme for Low Glitch Output
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Solution Overview
Problem
Current digital-to-analog converters (DACs) experience transient glitches due to timing mismatches between control signals, which degrade the accuracy of analog output and introduce noise, especially when using deglitch cells that are sensitive to process variations.
Innovation Solution
The implementation of individual column decoders for even and odd rows of current unit cells allows for independent control, using thermal decoders with coupled timing encoding to synchronize adjacent rows, enabling a 'count-up' and 'count-down' mechanism to minimize timing mismatches and eliminate glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If deglitch cells are used to reduce transient glitches, then signal integrity is improved, but the system becomes sensitive to process variations
Solution Approach 1:
The patent divides the array of current unit cells into multiple sub-arrays, with each sub-array controlled by its own dedicated column decoder. This segmentation allows independent control of timing for different groups of cells, enabling precise synchronization without requiring deglitch cells that are sensitive to process variations. The row decoder similarly controls rows of unit cells across all sub-arrays.
2Measurement precision
If individual column decoders are implemented for each row, then timing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the array into sub-arrays and assigns one column decoder per sub-array rather than one per row, reducing the total number of decoders while maintaining timing precision within each sub-array. This segmented approach balances complexity reduction with timing control accuracy.
Solution Approach 2:
Multiple rows of unit cells within a sub-array are merged under the control of a single column decoder, reducing the total decoder count. The row decoder then provides additional granularity by controlling individual rows within each sub-array, achieving timing precision through coordinated control rather than independent decoders for each row.
3Object-generated harmful factors
If coupled timing encoding is used to synchronize adjacent rows, then glitch current is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent implements preliminary timing alignment through coupled timing encoding in the decoder logic, where the timing relationships between control signals for adjacent rows are pre-synchronized. This preliminary action ensures that control signals are properly aligned before reaching the unit cells, eliminating the need for additional deglitch cells and reducing manufacturing complexity while still minimizing glitch current.
Data Source
AI summary
The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.