Current DAC Return-to-Zero Pulse Design for Clock Jitter Tolerance

The patent applies periodic action by using a return-to-zero (RZ) pulse with fixed pulse width to gate the DAC output current. Instead of continuous integration, the feedback pulse is periodically activated with a fixed duration that is calibrated to be insensitive to clock jitter. This periodic gating mechanism resolves the contradiction by maintaining the low power consumption benefits of continuous-time operation while eliminating jitter sensitivity through the fixed-width pulse approach.

The patent introduces an intermediary element - a calibrated fixed pulse width generator that produces RZ pulses with a predetermined width. This intermediary component acts as a mediator between the clock signal and the DAC output current, transforming the jitter-prone continuous signal into a controlled periodic pulse train. The calibration process adjusts the pulse width to achieve jitter insensitivity, and this intermediary structure adds minimal complexity while significantly improving jitter tolerance.

The patent applies preliminary action by performing calibration of the fixed pulse width during the manufacturing or initialization process. The pulse width is pre-calibrated to a specific value that minimizes intersymbol interference for the intended application. This preliminary calibration action eliminates the need for complex real-time adjustment mechanisms, and once calibrated, the system operates with fixed parameters that automatically reduce intersymbol interference without requiring ongoing calibration.