Current-Controlled Delay Line for Low Power ADC
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Solution Overview
Problem
Conventional delay circuits in signal converting circuits face issues with voltage differences leading to logic operation errors and increased power consumption, especially when generating digital codes, due to the reliance on voltage-control modes and numerous comparators.
Innovation Solution
A delay line comprising series-connected delay cells that transmit signals stage by stage based on a decided delay time during a sensing period, with outputs reset to a second level when the sensing period ends, used in conjunction with a load-sensing circuit and analog-to-digital converting device to convert analog voltage into digital codes, reducing power consumption and maintaining high precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If voltage-control mode delay circuits are used, then delay time can be adjusted, but voltage differences cause logic operation errors and increased power consumption
Solution Approach 1:
The patent replaces voltage-control mode with current-control mode for delay adjustment. Current-controlled delay cells use current signals to control delay time, eliminating voltage level differences and the need for level shifters, thereby reducing power consumption while maintaining adjustable delay functionality
Solution Approach 2:
The patent changes the control parameter from voltage to current. By using current-controlled delay cells instead of voltage-controlled ones, the system achieves delay adjustment without the power consumption penalties associated with voltage level matching and level shifter circuits
2Measurement precision
If numerous comparators are used for high-bit digital code generation, then conversion precision is improved, but power consumption increases significantly
Solution Approach 1:
The patent segments the conversion process into multiple stages using a multi-stage delay line architecture. Instead of using numerous comparators simultaneously, the system divides the conversion into sequential stages, each handling a portion of the precision requirement, thereby reducing the number of active comparators and overall power consumption
Solution Approach 2:
The patent employs periodic sampling and conversion cycles. The analog-to-digital converter operates in discrete time intervals with periodic reset and conversion phases, allowing the system to achieve high precision over time without requiring all comparators to operate continuously, thus reducing average power consumption
3Reliability
If level shifters are added to mediate voltage levels, then logic operation errors are reduced, but device complexity and power consumption increase
Solution Approach 1:
The patent replaces voltage-level mediation with current-level operation throughout the delay circuit. By maintaining consistent current control from input to output, the system eliminates the need for level shifter circuits, reducing both device complexity and power consumption while maintaining logic operation accuracy
Data Source
AI summary
A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELLx (0<x≦n). The delay cells DCELL1˜DCELLn are connected in series to each other. Each of the delay cells DCELLx is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal ty (0<y≦n) of a delay cell DCELLy among the delay cells DCELL1˜DCELLn used as output terminal of the delay line.