Current to digital converter circuit, optical front end circuit, computed tomography apparatus and method
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Solution Overview
Problem
Existing optical front end amplifiers in computed tomography applications face challenges in achieving a favorable noise-power tradeoff, often requiring increased power consumption or the use of expensive low threshold voltage transistors.
Innovation Solution
A current to digital converter circuit is proposed, incorporating an integrator amplifier, a quantizer circuit, a digital-to-analog converter circuit, and a controlled current source. This design allows for the integration of a current signal into a voltage signal, with the controlled current source providing an auxiliary current to rapidly recharge the output of the integrator amplifier, thereby improving settling time and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional front end amplifiers are used to achieve low noise performance, then noise performance is improved, but power consumption increases
Solution Approach 1:
The front end amplifier is segmented into two distinct stages: a first stage that integrates the photodiode current and a second stage that acts as a voltage amplifier. This segmentation allows each stage to be optimized independently, with the first stage consuming minimal power for integration and the second stage providing noise performance, thereby reducing total power consumption while maintaining low noise characteristics.
Solution Approach 2:
The patent employs periodic switching of the second stage amplifier, activating it only during specific time intervals when signal processing is required. This periodic operation reduces average power consumption compared to continuous operation of conventional single-stage amplifiers, while still achieving the necessary noise performance during active periods.
2Speed
If the settling time of the integrator amplifier is reduced, then conversion speed is improved, but noise performance deteriorates
Solution Approach 1:
The two-stage architecture separates the integration function (first stage) from the amplification function (second stage). The first stage can use a larger time constant for stable integration without noise concerns, while the second stage provides the necessary signal amplification and noise performance, effectively decoupling the settling time from noise performance degradation.
Solution Approach 2:
The first stage performs preliminary integration of the photodiode current over an extended period, accumulating charge without the noise amplification that would occur if a single stage operated at high speed. This preliminary integration action allows subsequent fast amplification in the second stage without compromising noise performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves improved noise performance with significantly reduced power consumption, allowing for faster settling times that are up to 4 to 20 times better than conventional methods, while maintaining the same noise performance.
Implementation Method 1
an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal
Implementation Method 2
a controlled current source coupled to the output of the integrator amplifier via a first switch controlled in function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier
Data Source
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AI summary
A current to digital converter circuit has an integrator amplifier (IAmp) with an input (12) adapted to receive a current signal (Ip) and an output (13) adapted to provide a voltage signal (Vout) as a function of an integration of the current signal (Ip), a quantizer circuit (Op2) with an input which is coupled to the output (13) of the integrator amplifier (IAmp) and with an output (14) adapted to provide a binary result signal (Scmp1) as a function of a comparison of the voltage signal (Vout) with at least a first reference voltage signal (Vref1), a digital-to-analog converter circuit (Dac) which is coupled in a switchable manner as a function of the binary result signal (Scmp1) to the input (12) of the integrator amplifier (IAmp), and a controlled current source (CCS) which is coupled to the output (13) of the integrator amplifier (IAmp) via a first switch (S1) which is controlled as a function of the binary result signal (Scmp1) such that an auxiliary current (Iaux) is supplied to the output (13) of the integrator amplifier (IAmp).