Current Doubler DC-DC Converter Sleep Mode Reserve Capacitor
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Solution Overview
Problem
Current doubler DC-DC converters face limitations in responsiveness to load transients and are stressed by reverse power transfer conditions, leading to inefficiencies and the need for expensive components.
Innovation Solution
The implementation of a fast-response current doubling DC-DC converter with a reserve capacitor and a controller that suspends primary switch array operation during a sleep mode, using the reserve capacitor to sustain voltage and reduce switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the primary switch array operates continuously to maintain output voltage, then the output voltage stability is improved, but the switching losses increase and responsiveness to load transients deteriorates
Solution Approach 1:
The patent implements periodic action by alternating between active mode (primary switch array operating) and sleep mode (primary switch array suspended). The controller periodically transitions between these modes based on load conditions, allowing the primary switch array to remain suspended during sleep mode while the reserve capacitor maintains output voltage, thereby reducing switching losses during light-load conditions while maintaining voltage stability when needed.
Solution Approach 2:
The patent applies preliminary action by pre-charging the reserve capacitor during active mode operation. This pre-stored energy in the reserve capacitor enables the system to quickly respond to load transients and maintain output voltage stability without requiring continuous operation of the primary switch array, thus reducing switching losses while being prepared to handle sudden load changes.
2Speed
If the primary switch array operates at high frequency to improve responsiveness to load transients, then the response speed is improved, but the switching losses increase
Solution Approach 1:
The controller implements periodic action by switching between active and sleep modes based on load conditions. During sleep mode, the primary switch array is suspended to eliminate switching losses during light-load conditions. The reserve capacitor, pre-charged during active mode, maintains output voltage stability. This periodic operation allows the system to achieve fast response when needed while minimizing switching losses during steady-state operation.
3Reliability
If high voltage-rated transistors are used to handle reverse power transfer conditions, then the reliability under stress is improved, but the device complexity and cost increase
Solution Approach 1:
The patent applies beforehand cushioning by introducing a reserve capacitor that absorbs and buffers reverse power transfer conditions. When reverse power flow occurs, the reserve capacitor absorbs the voltage spike and prevents it from reaching the transistors, thereby protecting them from excessive voltage stress. This allows the use of lower voltage-rated, less expensive transistors while maintaining reliability under reverse power transfer conditions.
Solution Approach 2:
The reserve capacitor serves as an intermediary element between the transformer and the output circuit. It mediates reverse power transfer conditions by absorbing voltage spikes and isolating the transistors from direct exposure to high voltage stress during reverse power flow. This intermediary protection allows the use of lower voltage-rated transistors while maintaining system reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the converter's responsiveness to load transients, reduces component stress during reverse power transfer, and maintains efficiency while allowing the use of lower voltage-rated transistors, thereby improving overall performance and cost-effectiveness.
Implementation Method 1
a transformer, first and second inductors coupled together at a first voltage output terminal
Implementation Method 2
uses the reserve capacitor to sustain a voltage at the first voltage output terminal
Data Source
AI summary
Improved current doubling DC-DC converters having an efficient sleep mode. An illustrative converter embodiment includes: a transformer, first and second inductors coupled together at a first voltage output terminal, a reserve capacitor coupled to a second output voltage terminal, a primary switch array, a secondary switch array, and a controller. The first and second inductors each have a drive terminal coupled to a respective terminal of the transformer secondary. The primary switch array operates to convert an input voltage into forward voltage pulses and reverse voltage pulses on the transformer primary. The secondary switch array selectively couples the first inductor's drive terminal to either a charge terminal of the reserve capacitor or to the second voltage output terminal. The controller at least temporarily suspends operation of the primary switch array during a sleep mode, and uses the reserve capacitor to sustain a voltage at the first voltage output terminal.