Switched-Capacitor Current-Frequency Converter Without Reset Noise
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Solution Overview
Problem
Traditional in-pixel ADC imagers face limitations such as reduced charge storage capacity due to shrinking pixel sizes, difficulties in generating wide enough reset pulse widths, and increased noise with deep submicron CMOS technology, leading to instability and accuracy issues.
Innovation Solution
A current-to-frequency converter using a switched capacitor and a Master-Slave Flip Flop with a DPDT switch network automatically reverses the integration capacitor's polarity at reference charge levels, eliminating the need for standard reset mechanisms and associated noise, while leveraging faster gate speeds for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to increase resolution, then imaging resolution is improved, but charge storage capacity deteriorates
Solution Approach 1:
The patent divides the charge accumulation function into multiple integration capacitors that can be sequentially activated. Instead of relying on a single large capacitor, the system uses multiple smaller capacitors (e.g., 2-4 capacitors) that are switched in series, effectively segmenting the storage function to achieve high capacity within limited pixel area.
Solution Approach 2:
The patent implements dynamic switching between multiple integration capacitors using switch networks controlled by a Master-Slave flip-flop. The system dynamically selects which capacitor to use based on accumulated charge levels, allowing the integration capacity to be effectively increased over time while maintaining small individual capacitor sizes suitable for miniaturized pixels.
2Ease of operation
If standard reset mechanisms are used to discharge integration capacitor, then charge level is reset, but reset noise is introduced
Solution Approach 1:
The patent extracts and eliminates the noisy reset pulse generation mechanism from the system. Instead of using active reset pulses that discharge the capacitor, the design allows the integration capacitor to naturally retain charge indefinitely, removing the source of reset noise entirely while maintaining the ability to read out and reset data digitally.
Solution Approach 2:
The system uses the natural properties of the integration capacitor to maintain charge without active reset intervention. The capacitor self-maintains its charge state through the switching mechanism, and reset is achieved through digital readout and re-initialization rather than active discharge pulses, making the system self-sufficient in maintaining charge integrity.
3Speed
If faster gate speeds are used in deep submicron CMOS, then circuit speed is improved, but reset pulse width control becomes difficult
Solution Approach 1:
The patent removes the reset pulse width control function from the analog domain entirely. By eliminating the need for precisely timed reset pulses, the system avoids the manufacturing precision challenges associated with controlling pulse widths in fast CMOS processes. Reset is handled in the digital domain where timing precision is less critical.
Solution Approach 2:
The patent replaces the mechanical/timing-based reset pulse system with a digital control system. Instead of relying on precisely timed analog pulses that are difficult to control in fast CMOS, the system uses digital logic (Master-Slave flip-flop) and switch networks that are inherently more suitable for high-speed CMOS operation, substituting the timing-critical mechanism with a logic-based control approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the well capacity of imagers, reduces reset noise, and maintains integration during switching events, improving the converter's performance and stability, even as semiconductor technology advances.
Implementation Method 1
A focal plane array typically includes a two-dimensional array of detector elements, or pixels, organized by columns and rows. It is common for a circuit or imager within a pixel to accumulate charge from a photo-diode, the charge corresponding to the flux of light of various wavelengths incident on the photo-diode.
Implementation Method 2
The well capacitor integrates photo-current from the detector diode over an integration interval. Once per frame, the voltage on the well capacitor is transferred to a sample-and-hold capacitor and then transferred out, line by line, to an Analog to Digital Converter (ADC)
Data Source
AI summary
According to one aspect, embodiments herein provide a current to frequency converter comprising a node configured to be coupled to a photodetector and to receive a photo-current from the photodetector, a capacitor having a first terminal and a second terminal and configured to accumulate electrical charge derived from the photo-current on the first terminal and the second terminal, a switch network configured to selectively couple one of the first terminal and the second terminal to the node, and a Master-Slave (MS) Flip Flop (FF) coupled to the switch network and configured to operate the switch network to toggle which of the first terminal and the second terminal is coupled to the node based on a voltage at the node.