Current Leveling in High-Speed Transmitter Drivers

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Solution Overview

Problem

High-speed digital data transmission faces performance limitations due to data-dependent switching noise propagating through power rails, causing timing jitter and degrading signaling performance in silicon-based transceiver circuits, especially at sub-20 picosecond pulse widths.

Innovation Solution

A current leveling strategy is implemented using an auxiliary drive signal with transitions where the main transmit signal lacks them, ensuring consistent current draw and reducing noise, which is achieved by deriving a serialized auxiliary stream from the input bit stream and synchronously supplying it to an auxiliary module with matched impedance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If conventional filtering strategies are used to suppress switching noise, then noise reduction is achieved, but data transmission rate and signaling performance are degraded

Engineering Contradiction:
Improveswitching noiseVSAvoiddata transmission rate
Core Design Contradiction:
Object-affected harmful factorsVSProductivity

Solution Approach 1:

The patent converts the harmful switching noise into a beneficial effect by using current leveling to make the noise uniform and independent of transmitted data. The auxiliary signal buffer generates controlled transitions that cancel out the harmful data-dependent variations in current draw, transforming the noise problem into a performance enhancement mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent changes the parameter of current draw by introducing an auxiliary signal that compensates for data-dependent current variations. By monitoring transitions in the transmit signal and generating corresponding auxiliary transitions, the system maintains a constant average current draw regardless of the transmitted data pattern, thereby eliminating switching noise without filtering.

Inventive Principle:
Principle #35Parameter changes

2Speed

If high current swings are used to achieve sub-20 picosecond pulse width, then signaling rate is improved, but timing jitter and performance degradation increase

Engineering Contradiction:
Improvesignaling rateVSAvoidtiming jitter
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent changes the temporal distribution of current draw by introducing auxiliary transitions that fill in the gaps between transmit signal transitions. This maintains a uniform current draw over time, preventing the current spikes that cause timing jitter while preserving the high signaling rate required for sub-20 picosecond pulse widths.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If data-dependent current variations are allowed to propagate through power rails, then circuit simplicity is maintained, but noise propagation and performance degradation occur

Engineering Contradiction:
Improvecircuit simplicityVSAvoidnoise propagation
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary auxiliary signal buffer that mediates between the data input and the power rail. This intermediary component generates compensating transitions that cancel out data-dependent current variations, preventing noise propagation through the power rails while maintaining overall circuit simplicity through the use of basic buffer logic.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9924246B2Transition replacement for current leveling in a high-speed transmitter
Publication Date: 2018.03.20 CREDO TECHNOLOGY GROUP LTD
  • US9924246B2 patent drawing
  • US9924246B2 patent drawing
  • US9924246B2 patent drawing

AI summary

An illustrative driver embodiment supplies an electrical transmit signal to an emitter module in response to an input bit stream. The illustrative driver embodiment includes: a voltage supply node which may be powered via a parasitic series inductance; a transmit signal buffer that drives the electrical transmit signal with current from the voltage supply node, the electrical transmit signal including transitions at bit intervals as dictated by the input bit stream; and an auxiliary signal buffer that supplies an auxiliary signal with current from the voltage supply node to an auxiliary module having an input impedance matched to an input impedance of the emitter module, the auxiliary signal having a transition at every bit interval where the electrical transmit signal lacks a transition.