Current Limit Element for ESD Protection in Semiconductor ICs
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Solution Overview
Problem
The existing RC trigger power clamp MOS ESD protection circuits face challenges in minimizing clamp voltage while maintaining low current consumption, as reducing clamp voltage leads to increased off-leakage current during normal operations, potentially damaging the CMOS inverter due to higher current loads and diode voltage constraints.
Innovation Solution
Incorporating a current limit element, such as a resistance or capacitance element, between the well region and the gate of the power clamp MOS, to limit current flow into the inverter, thereby increasing the well potential and facilitating the ON operation of the MOS transistor, thus reducing the risk of destruction and enabling low-voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length of the MOS is miniaturized and W size is increased to reduce clamp voltage, then the clamp voltage is reduced, but off-leakage current increases causing higher current consumption
Solution Approach 1:
A current limit element is introduced as an intermediary component between the well region and the gate of the power clamp MOS. This mediator limits the current flowing into the gate during normal operation, preventing excessive off-leakage current while maintaining the reduced clamp voltage characteristic achieved through miniaturized gate length and increased W size.
2Reliability
If the output of the CMOS inverter is supplied to the gate potential and well potential of the power clamp MOS to increase ESD discharge capability, then the ESD discharge capability is increased, but the load current through the PFET increases potentially destroying the inverter
Solution Approach 1:
The current limit element serves as a protective intermediary between the CMOS inverter output and the power clamp MOS gate/well. It allows sufficient current to flow during ESD events to maintain high discharge capability, while limiting the current during normal operation to prevent inverter destruction from excessive load.
Solution Approach 2:
The current limit element changes the current flow parameters dynamically - allowing high current during ESD events when the inverter output switches, while maintaining low current during normal standby operation. This parameter control resolves the contradiction between ESD capability and inverter protection.
3Reliability
If the well and source of the power clamp MOS are connected, then the substrate potential is increased facilitating parasitic bipolar operation, but the gate potential does not rise sufficiently reducing channel current
Solution Approach 1:
The current limit element is positioned between the well region and gate, acting as a selective mediator. It allows the well potential to rise sufficiently to activate parasitic bipolar operation while simultaneously controlling the gate potential to maintain adequate channel current flow, resolving the conflict between these two requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the risk of CMOS inverter destruction, enhances ESD discharge capability, and allows for low-voltage operation by limiting current flow and increasing the well potential, thereby preventing thermal destruction and improving parasitic bipolar operation.
Implementation Method 1
a current limit element which limits a current flowing into the inverter
Implementation Method 2
increases a potential in the well region to accelerate an ON operation of the MOS transistor
Implementation Method 3
an input time delay of the CMOS inverter occurs according to a time constant of the resistance element and the capacitance element
Implementation Method 4
the ESD surge current between the drain and the source can be flowed between a power supply and a ground
Data Source
AI summary
The present technology relates to a semiconductor integrated circuit which operates with a low voltage and is capable of preventing destruction of a protection circuit and a control method thereof. The semiconductor integrated circuit includes a resistance element and a capacitance element connected between a power supply line and a ground line in series, an inverter of which an input is connected between the resistance element and the capacitance element, a MOS transistor of which a gate electrode is connected to an output of the inverter and a drain electrode and a source electrode are respectively connected to the power supply line and the ground line, and a current limit element inserted between a well region where the MOS transistor is formed and the gate electrode. The present technology is applied to, for example, the protection circuit for preventing destruction of an internal circuit by ESD and the like.