Current Limit Circuit Using Feedback PMOS Reference
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices face challenges in maintaining a constant limiting current to suppress leakage current caused by short circuit faults between bit lines and word lines, as the threshold voltage of PMOS transistors fluctuates due to temperature and manufacturing variations, affecting reliability.
Innovation Solution
A current limit circuit comprising a PMOS transistor and a gate voltage generating circuit that uses feedback control with a second PMOS transistor of similar characteristics to maintain a constant limiting current, regardless of threshold voltage fluctuations, by adjusting the gate voltage to match the threshold voltage of the second PMOS transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a constant voltage is applied to the gate of the PMOS transistor to limit current, then the current limiting function is achieved, but the limiting current fluctuates with threshold voltage changes due to temperature and manufacturing variations
Solution Approach 1:
The patent implements a feedback mechanism where the gate voltage of the first PMOS transistor is dynamically adjusted based on the threshold voltage of a second PMOS transistor. The gate voltage generating circuit continuously monitors and adjusts the gate voltage to maintain a constant potential difference, thereby compensating for threshold voltage fluctuations and stabilizing the limiting current.
Solution Approach 2:
The patent changes the parameter being controlled from a fixed gate voltage to a dynamically adjusted gate voltage that compensates for threshold voltage variations. By using the threshold voltage of a second PMOS transistor as a reference and adjusting the gate voltage accordingly, the system maintains stable current limiting performance despite temperature and manufacturing variations.
2Reliability
If redundancy cells are used to replace faulty cells, then faulty cells with short circuit faults can be replaced, but leakage current from short circuit faults still flows in standby mode
Solution Approach 1:
The patent introduces an intermediate current limiting circuit between the bit line pre-charge voltage source and the equalizing circuit. This intermediary circuit actively limits the current flowing through bit lines during standby mode, preventing excessive leakage current from short circuit faults while allowing the redundancy replacement function to operate normally.
3Reliability
If the gate voltage is adjusted to compensate for threshold voltage fluctuations, then the limiting current can be stabilized, but the circuit complexity increases
Solution Approach 1:
The patent uses a second PMOS transistor as a reference device that copies or mimics the characteristics of the first PMOS transistor. By using this reference transistor to generate the gate voltage, the circuit automatically compensates for threshold voltage fluctuations without requiring complex external control circuits, thus balancing reliability improvement with acceptable circuit complexity.
Data Source
AI summary
A current limit circuit comprising: a current limit element for limiting an output current level to within a predetermined range of a limiting current and including a first PMOS transistor having a source to which a predetermined voltage is applied and a drain through which the output current is supplied; and a gate voltage generating circuit for generating a gate voltage by a feedback control such that a difference between the predetermined voltage and a gate voltage of the first PMOS transistor coincides with a threshold voltage of a second PMOS transistor having approximately the same characteristic as that of the first PMOS transistor in a state in which a predetermined current is flowing through the second PMOS transistor.