Input Current Limiter Frequency Loop for Fast Load Response

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional input current limit circuits in power electronics fail to respond quickly enough to load changes due to delays in voltage regulation, leading to overshoot and undershoot in input current, particularly in noisy environments with variable load conditions.

Innovation Solution

Implementing a frequency control loop that directly adjusts the clock frequency of processing cores, using an internal ADC and DVCO block to inject a virtual voltage drop, allowing for faster response to load changes and reducing input current ripple.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage regulation is used to limit input current, then input current limit is maintained, but response speed to load changes is slow

Engineering Contradiction:
Improveinput current limitVSAvoidresponse speed to load changes
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

Instead of regulating voltage to limit current (conventional approach), the patent inverts the control sequence by first adjusting frequency to quickly respond to load changes, then regulating voltage to maintain current limits. This inversion of control priority resolves the contradiction between fast response and current limiting.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent applies preliminary action by adjusting frequency before voltage regulation when load changes are detected. This preliminary frequency adjustment provides immediate response to load variations, preventing current overshoot/undershoot, while subsequent voltage regulation ensures current limits are maintained.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If voltage is adjusted first to limit input current, then current limit is maintained, but loading time of processing core increases

Engineering Contradiction:
Improveinput current limitVSAvoidloading time of processing core
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent inverts the conventional voltage-first approach by implementing frequency-first control. Frequency adjustment occurs before voltage regulation, significantly reducing the loading time of processing cores while still maintaining input current limits through subsequent voltage control.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

Frequency adjustment is applied as preliminary action before voltage regulation. This preliminary frequency change quickly adapts the processing core to new load conditions, reducing loading time, while voltage regulation follows to ensure current limits are not exceeded.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If frequency is increased for higher performance, then processing performance improves, but input current increases

Engineering Contradiction:
Improveprocessing performanceVSAvoidinput current
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic control by continuously adjusting both frequency and voltage based on real-time load conditions and current measurements. This dynamic coordination allows the system to maximize processing performance while maintaining input current within limits, resolving the trade-off between productivity and current consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes operating parameters (frequency and voltage) in a coordinated manner. Frequency is adjusted to meet performance requirements, while voltage is simultaneously regulated to ensure input current remains within limits. This dual parameter adjustment resolves the contradiction between performance and current consumption.

Inventive Principle:
Principle #35Parameter changes

4Stability of the object's composition

If voltage regulation alone is used, then output voltage is maintained, but input current ripple increases in noisy environments

Engineering Contradiction:
Improveoutput voltageVSAvoidinput current ripple
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

Frequency adjustment is applied as preliminary action before voltage regulation. This preliminary frequency stabilization reduces input current ripple by pre-adapting the processing core to load conditions, while subsequent voltage regulation maintains output voltage stability. The dual approach is particularly effective in noisy environments with variable loads.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamic coordination between frequency and voltage control. Frequency is adjusted to stabilize processing core operation and reduce current ripple, while voltage is simultaneously regulated to maintain stable output. This dynamic dual-control approach effectively suppresses input current ripple in noisy environments.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12468371B2Frequency-voltage control for input current limit circuit
Publication Date: 2025.11.11 NVIDIA CORP
  • US12468371B2 patent drawing
  • US12468371B2 patent drawing
  • US12468371B2 patent drawing

AI summary

Technologies directed to input current limiter (ICL) circuits with frequency control loops are described. One integrated circuit includes a processing core and an ICL circuit. The ICL circuit can limit an input current to the processing core within a current limit of the processing core. The ICL circuit can determine an input current and a supply voltage provided to the processing core at a first time. The ICL circuit can reduce a clock of the processing core from a first clock frequency to a second clock frequency with a linear frequency drop based on the current limit, the input current, and the supply voltage. value, the second value, and the third value. The first clock frequency corresponds to a first voltage, and the second frequency corresponds to a second voltage. The ICL circuit can reduce the clock to a third clock frequency corresponding to a third voltage.