Current Memory Cell Switching Scheme for Shorter Refresh Cycles
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Solution Overview
Problem
Current memory cells require frequent refresh periods to maintain a constant current supply, which can be inefficient and time-consuming.
Innovation Solution
A current memory cell design incorporating an amplifier, transistors, capacitors, and switching units that utilize control signals to alternate between charging and discharging periods, allowing for reduced refresh periods by maintaining voltage across capacitors and ensuring constant current supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional current memory cell periodically charges a capacitor during a refresh period to supply constant current, then the constant current supply is maintained, but the refresh period becomes long and operational efficiency decreases
Solution Approach 1:
The patent divides the current memory cell into two parallel branches: a first branch with a first capacitor for voltage storage and a second branch with a second capacitor for current storage. This segmentation allows independent operation of voltage charging and current maintaining functions, enabling the refresh period to be reduced while maintaining constant current supply reliability.
Solution Approach 2:
The first capacitor is charged to a reference voltage during a brief refresh period through a reference current source, preparing the voltage storage in advance. This preliminary voltage charging action enables the second capacitor to maintain constant current for an extended period without requiring continuous refreshing, thus reducing the effective refresh period.
2Productivity
If the refresh period is reduced to improve operational efficiency, then productivity increases, but maintaining constant current supply becomes more difficult
Solution Approach 1:
The first capacitor acts as an intermediary between the reference current source and the second capacitor. It converts the reference current into a stable reference voltage that controls the transistor gate, which in turn regulates the current through the second capacitor. This intermediary voltage storage mechanism enables rapid refreshing while maintaining precise constant current supply.
Solution Approach 2:
The patent replaces direct current charging mechanisms with voltage-based control through capacitors and transistors. By using voltage storage (first capacitor) to control current flow (second capacitor) through field-effect transistor gate control, the system achieves faster response and reduced refresh periods while maintaining current constancy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a decrease in the refresh period, allowing for more efficient and rapid maintenance of a constant current supply, improving the operational efficiency of current memory cells and digital-to-analog converters.
Implementation Method 1
a first capacitor coupled between the second node and the ground
Implementation Method 2
a second capacitor coupled between a third node and the ground
Data Source
AI summary
A current memory cell includes an amplifier, transistor, first and second capacitors, and first to third switching units. The amplifier includes first to third terminals. The transistor is coupled to first and second nodes, and ground. The first capacitor is coupled between the second node and ground. The second capacitor is coupled between a third node and ground. The first unit couples a current source to the first node during a first period and an output line to the first node during a second period. The second unit couples the first node to the second node during the first period. The third unit couples the first terminal to the second node and couples the second and third terminals to the third node during the first period, and couples the first terminal to the third node and couples the second and third terminals to the second node during the second period.