Current Mirror Biasing for Faster Low-Current Settling
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Solution Overview
Problem
Current-mirror circuits face challenges in achieving fast and precise output current settling times, particularly when a low input current is supplied by a large diode-connected transistor, leading to slow asymptotic behavior and increased settling time due to the operating point being close to the transistor's turn-off condition.
Innovation Solution
A method is introduced where a bias current is caused to flow in the diode-connected transistor, and this bias current is subtracted from the current flowing into the load, using additional current sources to shunt away the bias current, thereby shifting the operating point and improving the settling time without increasing transistor sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large diode-connected transistor is used to supply low input current, then the initial transient phase is sped up, but the final transient phase becomes very slow due to operating point close to turn-off condition
Solution Approach 1:
The patent applies preliminary action by introducing a bias current before the final settling phase. The bias current source provides an additional current path that预先 establishes a higher operating point for the diode-connected transistor, ensuring that even when the input current is low, the transistor operates in a region with sufficient transconductance to drive the settling process efficiently.
Solution Approach 2:
The patent changes the operating parameters of the diode-connected transistor by superimposing a bias current on top of the input current. This parameter change shifts the operating point away from the turn-off region, maintaining higher transconductance throughout the settling process and thereby reducing the final transient phase duration.
2Speed
If transistor size is increased to improve current driving capability, then transient response improves, but chip area increases
Solution Approach 1:
Instead of changing the physical size (geometry) of the transistors, the patent changes the electrical parameters by introducing a bias current. This allows the same transistor size to achieve faster transient response by operating at a higher current level, thereby improving speed without increasing chip area.
Solution Approach 2:
The patent effectively creates a current copy mechanism where the bias current mirrors the input current but adds an offset component. This copied current path allows the circuit to benefit from higher current levels (faster settling) without requiring larger transistor dimensions, thus avoiding area increase.
Data Source
AI summary
A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.