Current-Mirror Delay Line for Faster Die-to-Die Interconnect
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional delay lines suffer from parasitic resistance and capacitance that limit their speed and delay range, consuming excessive power and failing to meet performance requirements.
Innovation Solution
A high-speed delay line design that eliminates components from the signal path by using external current mirrors to control delay and duty cycle, employing PMOS and NMOS current mirror circuits to mitigate parasitic effects and optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If delay buffers and delay control current or capacitor arrays are used in the delay line, then delay control functionality is achieved, but parasitic resistance and capacitance increase, decreasing maximum signal speed and delay coverage range
Solution Approach 1:
The patent extracts the delay control functionality from the signal path by using external current mirrors that control the delay line from outside. The current mirrors are connected to control nodes of the delay elements rather than being part of the main signal path, thereby eliminating parasitic resistance and capacitance that would otherwise be introduced by delay buffers and control arrays within the signal path.
Solution Approach 2:
The patent introduces current mirrors as intermediary components that mediate between the control signals and the delay line. These current mirrors convert control voltages into control currents that adjust the delay elements without directly placing resistive or capacitive components in the signal path, thus maintaining signal speed while achieving delay control.
2Adaptability or versatility
If delay buffers and delay control current or capacitor arrays are used in the delay line, then delay control functionality is achieved, but power consumption increases
Solution Approach 1:
The patent extracts the power-consuming delay control components from the signal path and places them externally. The current mirrors are driven by control voltages that switch current sources on and off, consuming power only when delay adjustment is needed, rather than continuously powering delay buffers and control arrays throughout the signal path.
Solution Approach 2:
The patent employs periodic or switched control of the current mirrors through digital control signals. The current sources are activated only when delay reconfiguration is required, rather than maintaining continuous power consumption associated with traditional delay buffers and control arrays that must remain active throughout operation.
3Adaptability or versatility
If components are placed in the signal path for delay control, then delay adjustment is possible, but device complexity and parasitic effects increase
Solution Approach 1:
The patent extracts delay control components from the signal path and positions them externally. The current mirrors and control current sources are placed outside the main signal flow, connected only at control nodes, thereby reducing signal path complexity while maintaining full delay adjustability through external control mechanisms.
Data Source
AI summary
Systems and methods are provided for a delay line circuit that comprises a delay line core and a first current mirror circuit. The delay line core includes a plurality of inverters connected in series. Each of the plurality of inverters is coupled to a first common node. The first current mirror circuit includes a first current source configured to generate a first digital-to-analog (DAC) current, a first transistor coupled to the first current source, and a plurality of first controlling transistors coupled to the first transistor and the first common node. The plurality of first controlling transistors generates a first mirror current at the first common node based on the first DAC current. A delay time of the delay line core is controlled based on the first mirror current.