Low Voltage Current Mirror with Dynamic Element Matching
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Solution Overview
Problem
Conventional current mirrors face challenges in low voltage operation, accuracy of current ratio, high area overhead, and limited output impedance due to low power supply voltage and transistor mismatch, making them unsuitable for distributed current sensing in integrated circuits.
Innovation Solution
A low voltage current mirror circuit is designed with a first pair of transistors, a second pair in cascode, and a switching network with dynamic element matching, along with a source follower and multiple power supply nodes to achieve high accuracy and low area consumption, allowing for proportional output current generation even at low input voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional current mirror structures are used, then current amplification is achieved, but output impedance is limited and voltage headroom is insufficient for low voltage operation
Solution Approach 1:
The current mirror is divided into multiple independent transistor pairs (first pair M0-M1, second pair M2-M3, third pair M4-M5) connected in cascade. Each pair operates independently to provide current amplification stages, allowing the overall circuit to achieve high output impedance while maintaining low voltage operation through distributed voltage drops across stages.
Solution Approach 2:
The patent transitions from a single-stage current mirror to a multi-stage cascaded structure, adding the dimension of multiple amplification stages. This dimensional expansion allows each stage to contribute to current amplification while sharing the voltage headroom requirement, effectively increasing output impedance without proportionally increasing voltage consumption.
2Measurement precision
If simple current mirror with single transistor pair is used, then circuit area is minimized, but current ratio accuracy is poor due to transistor mismatch
Solution Approach 1:
Each transistor pair (M0-M1, M2-M3, M4-M5) is designed with specific width ratios to achieve precise current multiplication factors (15:1, 10:1, 5:1 respectively). The local geometry of each transistor is optimized for its specific function, allowing high overall accuracy through composition of multiple precise local transformations rather than relying on a single large transistor pair.
Solution Approach 2:
Multiple current mirror pairs are merged in cascade to achieve both high current ratio accuracy and area efficiency. The combined effect of three pairs with ratios 15:1, 10:1, and 5:1 produces an overall multiplication factor of 750:1, achieving superior accuracy through composition while using less total area than a single large-ratio mirror would require.
3Reliability
If multiple transistor pairs in cascode are used, then output impedance is increased, but voltage headroom requirement increases
Solution Approach 1:
The patent employs dynamic element matching with switching networks that periodically interchange connections between transistor pairs. This dynamic reconfiguration allows the circuit to maintain high output impedance characteristics while adapting to varying voltage conditions, effectively managing voltage headroom requirements through time-varying topology optimization.
Solution Approach 2:
The switching network dynamically changes the effective transistor pair connections based on operating conditions. By periodically altering which transistor pairs are active and how they are connected, the circuit maintains high output impedance while adjusting voltage headroom consumption to match available supply voltage, enabling low-voltage operation without sacrificing impedance performance.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.