Current-Mirror ESD Clamping Circuit Prevents Gate Leakage
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Solution Overview
Problem
Conventional electrostatic discharge (ESD) clamping circuits face significant gate leakage issues due to the thinning gate layer in advanced semiconductor processes, leading to unstable voltage and improper conduction, resulting in undesired power consumption and potential maloperation.
Innovation Solution
A current-mirror-based ESD clamping circuit is introduced, comprising a first and second power terminal, a current-mirror-based ESD detector, a driver, and an ESD clamping element, utilizing a resistor and semiconductor capacitor to determine voltage levels and generate driving signals for proper ESD operation, thereby preventing gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a MOS capacitor with a thin gate layer is used in advanced semiconductor processes, then the circuit can operate at higher integration levels, but gate leakage increases causing power consumption and voltage instability
Solution Approach 1:
The patent extracts the capacitor from the traditional ESD clamping circuit configuration and replaces it with a dedicated detection circuit comprising a detector and controller. This separation removes the problematic gate leakage source while preserving the ESD protection function, as the detector uses high-impedance nodes that do not require thin-gate MOS capacitors.
Solution Approach 2:
The patent introduces an intermediary detection circuit between the ESD event and the clamping response. The detector monitors voltage at high-impedance nodes and triggers the clamping element only when ESD is detected, rather than continuously engaging the capacitor. This intermediary mechanism eliminates the need for the capacitor to maintain voltage blocking through a thin gate layer.
2Area of stationary object
If the gate layer thickness is reduced to increase integration density, then more circuit elements can be packed, but voltage stability deteriorates due to leakage
Solution Approach 1:
The detection circuit utilizes the inherent high-impedance nodes already present in the ESD clamping circuit architecture. By detecting voltage changes at these existing nodes rather than introducing new capacitive elements, the circuit achieves ESD detection without adding components that would require thin gate layers, thus maintaining voltage stability while preserving integration density.
3Device complexity
If a conventional capacitor-based ESD clamping circuit is used, then the circuit structure is simple, but the voltage at the input end becomes unstable due to gate leakage
Solution Approach 1:
The patent implements feedback by having the detector continuously monitor the voltage at high-impedance nodes and feed this information to the controller. The controller adjusts the clamping element's operation based on the detected voltage levels, ensuring stable operation even when the gate layer is thin. This closed-loop control compensates for leakage effects without requiring a complex circuit structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The current-mirror-based ESD clamping circuit effectively prevents gate leakage, stabilizes voltage, and reduces energy loss and maloperation risks by accurately controlling the conduction path during ESD events.
Implementation Method 1
the capacitor 140 blocks DC voltage while the voltage of the input end of the inverter 150 is a high voltage
Implementation Method 2
the switch 160 is conductive due to the high voltage and carries out electrostatic discharge
Data Source
AI summary
The present invention discloses a current-mirror-based electrostatic discharge (ESD) clamping circuit comprising: a first power terminal; a second power terminal; a current-mirror-based ESD detector; a driver; and an ESD clamping element. The current-mirror-based ESD detector includes: a resistor coupled between the first power terminal and a detection-output-terminal; a semiconductor capacitor coupled between the detection-output-terminal and an ESD triggered current mirror; and the ESD triggered current mirror operable to electrically connect the semiconductor capacitor and/or the detection-output-terminal with the second power terminal according to the level of a driving signal under an ESD operation. The driver is operable to generate the driving signal according to the voltages of the detection-output-terminal and the first and second power terminals. The ESD clamping element is operable to provide a conducting path from the first power terminal to the second power terminal according to the level of the driving signal under the ESD operation.