Selectable Current Mirror Switching With Glitch Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Selectable output current mirrors with degeneration resistors in electronic devices experience electrical glitches due to current 'kick back' when switching circuitry is turned on, causing sudden voltage changes and affecting current generation in output legs.
Innovation Solution
Incorporating a series combination of a degeneration resistor and a degeneration path switch between the voltage source and the source terminal of the output leg transistor, along with glitch mitigation circuitry to maintain a substantially-constant voltage during transitions, and using switch control circuitry to enable and disable the output leg.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a degeneration resistor is added to reduce flicker noise, then noise performance is improved, but electrical glitches occur during switching transitions
Solution Approach 1:
The glitch mitigation circuitry is enabled before the switching transition occurs and remains active during the transition. This preliminary action maintains the source terminal voltage at a constant level (VSS + IOUT × RD) during the critical switching period, preventing the sudden voltage change that causes the electrical glitch while allowing the degeneration resistor to continue reducing flicker noise.
2Productivity
If switching circuitry is enabled to generate output current, then current generation capability is improved, but sudden voltage changes cause glitches
Solution Approach 1:
The glitch mitigation circuitry acts as an intermediary between the switching circuitry and the source terminal voltage. When the drain path switch is enabled to generate output current, the glitch mitigation circuitry simultaneously activates to maintain a constant voltage at the source terminal, mediating the transition and preventing the harmful voltage spike that would otherwise cause the electrical glitch.
3Productivity
If the degeneration path switch is turned on to enable current flow, then output current is generated, but charge accumulation causes transient voltage changes
Solution Approach 1:
The glitch mitigation circuitry employs feedback control to maintain the source terminal voltage at a predetermined level (VSS + IOUT × RD). The circuit continuously monitors the voltage and adjusts the glitch mitigation current accordingly, providing negative feedback that counteracts charge accumulation effects and prevents transient voltage changes when the degeneration path switch is activated.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces or eliminates electrical glitches by maintaining a constant voltage during transitions, preventing sudden changes that affect current generation and improving the stability of output currents in electronic devices.
Implementation Method 1
Any charge leaving or accumulating in the channel may cause a reflected change in charge at the transistor's gate terminal, due to a capacitance that exists between the source and gate terminals
Data Source
AI summary
A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror. The selectable output current mirror may also include switch control circuitry configured to selectively enable and disable the output leg from generating the output current by selectively enabling and disabling the drain path switch and the degeneration path switch and glitch mitigation circuitry coupled to the second non-gate terminal of the output leg transistor and configured to maintain the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch.