Current Mirror Layout for Gradient-Resistant Output Matching
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Solution Overview
Problem
Current semiconductor devices with current mirror circuits face output capability variations due to gradient effects in manufacturing processes, such as angle differences in light sources and etching, leading to inconsistent circuit characteristics among voltage-to-current converters.
Innovation Solution
A semiconductor device layout with a substrate arranged in a line-symmetrical and point-symmetrical array configuration, where first, second, and third voltage-to-current converters are strategically positioned to minimize gradient effects, ensuring synchronized and symmetrical sub-converter enablement and disablement, thereby maintaining consistent output capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If all transistors of the voltage-to-current converter are aligned in a row and on the same OD region to share the oxide diffusion region, then the area utilization ratio is increased, but the output capability variation among different voltage-to-current converters increases due to gradient effects in the manufacturing process
Solution Approach 1:
The patent applies asymmetry by intentionally introducing dummy transistors to create an asymmetrical layout that compensates for the symmetrical gradient effects. The dummy transistors are added to specific voltage-to-current converters based on their position in the array, creating an intentional asymmetry that balances the overall output capability across all converters while maintaining high area utilization through shared OD regions.
Solution Approach 2:
The patent applies local quality by adding dummy transistors selectively to specific voltage-to-current converters rather than uniformly to all converters. The number of dummy transistors varies depending on the position of each converter in the array, creating local adjustments that compensate for position-dependent gradient effects and achieve uniform output capability across the entire array.
2Area of moving object
If voltage-to-current converters are arranged in a compact layout to reduce total area, then area utilization is improved, but manufacturing precision deteriorates due to gradient effects from light source angle differences and etching variations
Solution Approach 1:
The patent applies parameter changes by modifying the effective transistor count parameter through the addition of dummy transistors. This changes the electrical characteristics of specific voltage-to-current converters to compensate for manufacturing variations, allowing the circuit to achieve consistent output capability despite gradient effects introduced by compact layout and manufacturing process variations.
Solution Approach 2:
The patent applies copying by creating dummy transistors that replicate the structure and function of real transistors. These dummy transistors are copied from the standard transistor design and integrated into specific voltage-to-current converters to provide the necessary compensation without requiring new transistor designs or complex manufacturing processes.
3Area of moving object
If transistors are aligned on the same OD region to reduce layout area, then area utilization ratio is improved, but output current stability deteriorates due to different circuit characteristics from gradient effects
Solution Approach 1:
The patent applies asymmetry by introducing dummy transistors to create an asymmetrical configuration that compensates for the symmetrical gradient effects. The dummy transistors are strategically added to specific voltage-to-current converters based on their position, creating an intentional asymmetry that balances the output current stability across all converters while maintaining compact layout with shared OD regions.
Data Source
AI summary
A semiconductor device includes a substrate, two first voltage-to-current converters, two second voltage-to-current converters and two third voltage-to-current converters. The substrate includes six layout regions arranged as an array having a plurality of columns and a plurality of rows, the array is line-symmetrical with respect to a first axis and a second axis which are perpendicularly intersected at an array center point of the array. The two first voltage-to-current converters, the two second voltage-to-current converters and the two third voltage-to-current converters are respectively arranged in the six layout regions. With respect to the array center point, layouts of the two first voltage-to-current converters are point-symmetrical, layouts of the two second voltage-to-current converters are point-symmetrical, and layouts of the two third voltage-to-current converters are point-symmetrical. Along the direction of the first axis, the two third voltage-to-current converters are between the two first voltage-to-current converters and the two second voltage-to-current converters.