Current Mirror Load Switch for Shuntless Overcurrent Limiting
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Solution Overview
Problem
Existing integrated circuits face challenges in accurately detecting and limiting switchable load currents due to the need for precise shunt resistor design, which results in additional power losses and complexity, especially when trying to prevent thermal destruction during faults like short circuits.
Innovation Solution
The integration of a mirror transistor that tracks the source-drain voltage of a main transistor, allowing for proportional current detection and limitation without the need for a shunt resistor, thereby reducing power losses and simplifying evaluation electronics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a shunt resistor is integrated in the ASIC for current detection, then current limitation function is achieved, but additional voltage drop and power loss occur
Solution Approach 1:
The patent uses a mirror transistor that replicates the electrical characteristics of the main power transistor to create a scaled-down version of the load current. This current mirror approach allows accurate current detection without requiring a physical shunt resistor in the main current path, thereby eliminating the additional voltage drop and power loss that would be caused by the shunt resistor.
2Measurement precision
If the shunt resistor design is made more exact for precise current detection, then measurement precision improves, but device complexity and cost increase
Solution Approach 1:
Instead of using a precisely designed shunt resistor, the patent creates a current copy through the mirror transistor that replicates the main transistor's behavior. This current mirror technique provides precise current detection through proportional scaling, eliminating the need for complex high-precision resistor designs and their associated calibration requirements.
Solution Approach 2:
The mirror transistor acts as an intermediary that transfers information about the main current to the detection circuitry through a scaled-down proportional current. This intermediary approach allows accurate current measurement without directly inserting a shunt resistor into the main current path, simplifying the overall design.
3Reliability
If a shunt resistor is used for current detection, then current limitation is enabled, but additional space and cost are required
Solution Approach 1:
The current mirror technique creates a proportional copy of the load current through the mirror transistor, enabling current detection and limitation functionality without requiring external shunt resistors on the circuit board. This integration approach eliminates the additional space requirements for external components while maintaining the current limitation capability.
4Loss of energy
If the shunt resistor value is reduced to minimize power loss, then power efficiency improves, but signal evaluation becomes more difficult
Solution Approach 1:
The patent copies the current signal through the mirror transistor relationship, where the mirror current is proportional to the load current based on the transistor width ratio. This current copying mechanism provides sufficient signal level for easy evaluation without requiring large shunt resistor values, thus maintaining both low power loss and easy signal detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the need for external shunt resistors, reduces total resistance, and enables precise current detection and limitation, effectively preventing thermal destruction during overcurrent events without additional power losses.
Implementation Method 1
a coupling circuit, which is electrically connected to drain terminals of the main transistor and of the mirror transistor and is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor
Implementation Method 2
a gate control circuit, which is electrically connected to the gate terminal of the main transistor and is configured to limit the load current through the main switch on the basis of a drain current through the mirror transistor
Data Source
AI summary
A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.