Current Mirror Level Shifter With Suspended PMOS for Low Leakage

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Solution Overview

Problem

Current level shifters in the semiconductor industry face issues with power consumption and leakage, leading to inefficiencies and signal delays, particularly in miniaturized consumer electronic devices and IC memory cards, where complex structures and high device counts exacerbate these problems.

Innovation Solution

A simplified current mirror level shifter design is introduced, featuring a pair of PMOS and NMOS transistors with a suspended PMOS and a voltage shifter PMOS to reduce power consumption and leakage, utilizing a Vm node to couple gates and a Va node to improve performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a conventional current mirror level shifter is used, then voltage level translation is achieved, but power consumption increases and leakage current occurs

Engineering Contradiction:

Improvepower consumptionVSAvoidsignal delay

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent extracts and removes the cross-couple structure from the conventional level shifter circuit. By taking out this structure, the patent eliminates the fighting issue between PMOS and NMOS transistors that causes excessive power consumption and charge pump leakage, while maintaining the voltage level translation function through the simplified current mirror configuration

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent converts the harmful leakage current issue into a benefit by strategically placing suspension nodes and adjusting transistor gate voltages. The suspension nodes are positioned to block DC current paths that cause leakage, while the adjusted gate voltages ensure proper transistor switching, thereby converting potential harmful leakage into improved circuit performance with reduced power consumption

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If the cross couple structure is used in level shifter, then voltage level translation is achieved, but power consumption increases due to fighting issue

Engineering Contradiction:

Improvevoltage level translationVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If conventional level shifter structure is used, then voltage level translation is achieved, but area consumption increases

Engineering Contradiction:

Improvevoltage level translationVSAvoidarea consumption

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the functions of multiple transistors into a more compact current mirror configuration. By combining the voltage level translation function with the current mirror structure and eliminating redundant cross-couple transistors, the patent achieves the same voltage level translation capability with reduced transistor count and smaller circuit area

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The current mirror transistors in the patent serve multiple functions simultaneously: they perform current mirroring, voltage level translation, and signal buffering. This multi-functionality eliminates the need for separate dedicated structures, thereby reducing overall area consumption while maintaining reliable voltage level translation

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Loss of energy

If simplified current mirror level shifter is used, then power consumption is reduced, but device complexity needs to be managed

Engineering Contradiction:

Improvepower consumptionVSAvoiddevice structure

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent changes the operational parameters of the transistors, specifically adjusting gate voltages and introducing suspension nodes at strategic points. These parameter changes enable the simplified current mirror structure to achieve low power consumption by blocking DC current paths, while the changes are implemented in a way that maintains circuit functionality without introducing excessive complexity

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8653877B2Current mirror modified level shifter

Publication Date: 2014.02.18 NATIONAL TSING HUA UNIVERSITY

AI summary

A current mirror modified level shifter includes a pair of PMOS including a PMOS (MPL) and a PMOS (MPR), wherein a Vot node connected to a drain of the PMOS (MPR); a pair of NMOS including NMOS (MNL) and a NMOS (MNR), wherein sources of the PMOS (MPL) and the PMOS (MPR) are coupled to a high voltage (HV), respectively; gates of the PMOS (MPL) and the PMOS (MPR) coupled together through a Vm node which located between the gates of the PMOS (MPL) and the PMOS (MPR); and a suspended PMOS (MPM) coupled to drain of the PMOS (MPL), the Vm node being coupled to a Va node between drain of the suspend PMOS (MPM) and drain of the NMOS (MNL).