Current Mirror Mismatch Checking Through Transistor Parameter Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current mirror circuits in semiconductor devices can experience mismatches between input and output currents, leading to malfunctions and reduced manufacturing yields, which are not effectively addressed by existing technologies.
Innovation Solution
A system and method to analyze current mirror circuits for mismatches before manufacturing, adjusting the design if a mismatch exceeds a predetermined threshold, ensuring high yield by modifying the circuit to reduce discrepancies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current mirror circuits are used to generate replicated or scaled output currents, then the circuit provides stable current for other semiconductor circuits, but mismatches between input and output currents occur leading to malfunctions and reduced manufacturing yields
Solution Approach 1:
The patent applies preliminary action by calculating and determining optimal transistor width parameters before manufacturing the semiconductor device. The method computes width ratios for master and slave transistors based on desired current ratios and process parameters, then uses these pre-determined dimensions to fabricate the current mirror circuit. This upfront calculation ensures accurate current matching is built into the device structure before production, preventing mismatches rather than correcting them after manufacturing.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting transistor width parameters based on calculated optimal values. The method modifies the width-to-length ratios of master and slave transistors according to computed parameters that account for process variations and desired current scaling. By changing these geometric parameters during design based on mathematical optimization, the circuit achieves precise current mirroring despite manufacturing tolerances.
2Reliability
If transistor parameters are adjusted to reduce current mismatch, then current matching accuracy improves, but the design complexity and manufacturing process become more complicated
Solution Approach 1:
The patent replaces complex iterative manual design adjustments with an automated mathematical calculation system. Instead of relying on trial-and-error design modifications or complex simulation iterations, the method uses closed-form mathematical equations to directly compute optimal transistor dimensions. This substitution of computational mathematics for iterative design processes reduces complexity while maintaining high accuracy in current matching.
Solution Approach 2:
The patent simplifies design complexity by systematically varying transistor width parameters according to mathematically determined relationships. Rather than adjusting multiple parameters independently through complex optimization, the method establishes direct proportional relationships between transistor widths and desired current ratios, reducing the design space to a few key parameter calculations that can be performed analytically.
Data Source
AI summary
A method includes calculating a mismatch value between an input current associated with a master transistor of a current mirror circuit and a second current associated with a second transistor of the current mirror circuit, comparing the mismatch value to a predetermined mismatch threshold, and generating a comparison result that specifies whether the mismatch value exceeds the predetermined mismatch threshold. The parameter associated with the first transistor or the second transistor is modified when the mismatch value exceeds the predetermined mismatch threshold.