Current Mirror Circuits Sharing Reference Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current mirror circuits in ICs face challenges in maintaining identical output currents due to variations in threshold voltages and constants of transistors, leading to uneven performance in display apparatuses using LEDs or OLEDs, especially when sharing a common current source across different ICs.
Innovation Solution
The implementation of a current mirror circuit design that includes multiple identical transistors connected to a current generating circuit with a reference voltage, ensuring that output currents are equalized by mirroring currents through a structured arrangement of PMOS and NMOS transistors across different ICs, thereby minimizing differences in output currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current mirror circuits in different ICs share the same current source, then current copying function is achieved, but output current uniformity deteriorates due to transistor parameter variations
Solution Approach 1:
The patent introduces a reference voltage node as an intermediary that both current mirror circuits share. Instead of directly sharing the current source which amplifies transistor variations, the circuits share a stable reference voltage that serves as a common reference point, thereby maintaining current copying accuracy while reducing the impact of manufacturing variations on output uniformity
Solution Approach 2:
The patent changes the reference parameter from directly shared current to shared reference voltage. By converting the current reference to a voltage reference that both circuits can access, the system maintains the current copying function while the voltage parameter remains more stable across different ICs, compensating for transistor parameter variations
2Device complexity
If transistor threshold voltages and constants are assumed identical, then current mirror function is simplified, but output current difference increases in practice
Solution Approach 1:
The patent implements a feedback mechanism where the reference voltage is derived from the actual current flowing through the reference transistor. This feedback loop allows the circuit to automatically compensate for transistor parameter variations, maintaining output current equality without requiring complex manual calibration or assuming identical transistor parameters
3Adaptability or versatility
If multiple current mirror circuits share a common current source, then device integration is improved, but current variation across circuits worsens
Solution Approach 1:
The patent uses reference voltage as an intermediary that decouples the direct current sharing relationship. Multiple current mirror circuits can share the same reference voltage node independently, allowing device integration and adaptability while the voltage intermediary prevents current variations from propagating across different ICs
Solution Approach 2:
The patent segments the current reference function into separate voltage references that can be independently accessed by different current mirror circuits. Each circuit maintains its own current copying function while sharing the common voltage reference, enabling modular integration across multiple ICs with improved current consistency
Data Source
AI summary
A current mirror circuit, receiving an input current and outputting a plurality of mirroring currents, comprising: a first transistor, wherein a control terminal and a first terminal of the first transistor are connected to a first mirroring current of the input current; at least one second transistor, wherein a control terminal and a first terminal of the at least one second transistor are connected to the at least one second mirroring current of the input current; and a plurality of third transistors, outputting the plurality of mirroring currents from first terminals of the plurality of third transistors, wherein control terminals of the plurality of third transistors are connected to control terminals of the first transistor and the at least one second transistor. The first transistor, the at least one second transistor and the plurality of third transistors are identical.