Semiconductor Current Mirror Transistor Layout for Output Error Reduction
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Solution Overview
Problem
Current semiconductor devices face significant challenges in minimizing output current errors due to variations in transistor distances, which affect the accuracy and reliability of current sources in current mirror configurations.
Innovation Solution
A semiconductor device layout is implemented where multiple transistors are arranged around a central transistor at equal distances, with symmetric arrangements and uniform wiring structures to minimize variations in output current errors, ensuring consistent current supply capabilities across all transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are arranged in a current source cell matrix with fixed layout, then device complexity is reduced and manufacturing is simplified, but output current errors occur due to fabrication variations and distance-dependent variations
Solution Approach 1:
The patent applies asymmetry by strategically positioning dummy transistors at specific locations around the reference transistor rather than using uniform symmetric distribution. The dummy transistors are placed at distances of 0μm, 5μm, and 10μm in specific directions to counteract the asymmetric effects of fabrication variations and wiring resistance gradients, thereby improving current matching accuracy without requiring complete layout symmetry
Solution Approach 2:
The patent changes the parameter of transistor distance by introducing dummy transistors at multiple distance levels (0μm, 5μm, 10μm) from the reference transistor. This parameter variation allows the layout to compensate for distance-dependent current variations and fabrication process variations, improving output current accuracy while maintaining manufacturing simplicity
2Adaptability or versatility
If transistors are positioned at varying distances from the reference element, then layout flexibility is improved, but output current errors increase due to distance-dependent fabrication variations
Solution Approach 1:
The patent utilizes parameter changes by deliberately varying the distance parameter of dummy transistors from the reference element (0μm, 5μm, 10μm). This controlled parameter variation compensates for distance-dependent fabrication variations and wiring resistance effects, improving current source accuracy while preserving layout flexibility for different design requirements
3Area of stationary object
If current source cells are arranged in a dense matrix, then area efficiency is improved, but linearity deteriorates due to variations at the two ends of the matrix
Solution Approach 1:
The patent applies segmentation by dividing the current source cell matrix into multiple blocks arranged symmetrically with respect to the center of the matrix. Each block contains current source cells that are independently configured with dummy transistors, allowing the overall matrix to maintain high density while each segment preserves linearity and compensates for edge effects through localized dummy transistor placement
Data Source
AI summary
Disclosed is a semiconductor device including transistors B on an output side of a current mirror, arranged uniformly in a surrounding area of a transistor A on an input side of the current mirror. The transistors B are arranged at equal distances, adjacently to the transistor A, on both sides of the transistor A.