Current Mirror Transistor Layout Asymmetry for Mask Misalignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with current mirror structures are prone to performance degradation due to mismatching errors caused by misalignment of masks during the manufacturing process, leading to inconsistent transistor configurations and altered threshold voltages and current characteristics.
Innovation Solution
A current mirror semiconductor device and layout method that shifts the layout of transistors in a mirror structure to ensure identical misalignment conditions across all transistors, minimizing mismatch errors and maintaining consistent performance by arranging PMOS and NMOS transistors in a specific serial and mirrored configuration within N well and P-type substrate regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are arranged in a symmetric mirror structure, then device performance consistency is improved, but mask misalignment errors cause mismatching that degrades transistor performance
Solution Approach 1:
The patent applies asymmetry by intentionally designing the current mirror structure with different orientations for the first and second transistors. Specifically, the first transistor has its source-drain direction aligned with a first direction, while the second transistor has its source-drain direction aligned with a second direction that is different from the first direction. This asymmetric arrangement ensures that both transistors experience identical mask misalignment conditions during fabrication, thereby eliminating mismatching errors and improving performance consistency despite the asymmetric layout.
2Ease of manufacture
If symmetric layout is used for current mirror transistors, then manufacturing simplicity is improved, but mismatch errors increase due to different misalignment conditions
Solution Approach 1:
The patent deliberately introduces asymmetry in the layout orientation of the current mirror transistors. The first transistor is oriented with its source-drain direction along a first direction, while the second transistor is oriented with its source-drain direction along a second direction. This asymmetric configuration, while appearing more complex than symmetric layout, actually simplifies manufacturing by ensuring both transistors are subjected to the same misalignment conditions, thereby improving matching accuracy without significantly increasing manufacturing complexity.
3Adaptability or versatility
If transistors are positioned at different locations in the wafer, then design flexibility is improved, but performance variation occurs due to wafer position differences
Solution Approach 1:
The patent applies local quality by focusing on the local orientation relationship between the first and second transistors within the current mirror structure. Rather than relying on global wafer position uniformity, the invention ensures that locally, both transistors experience identical misalignment conditions through their specific directional arrangement. This local optimization approach maintains performance uniformity while allowing flexible positioning of the current mirror structure anywhere on the wafer.
Data Source
AI summary
A semiconductor device and a layout method of the same reduce a mismatch in a semiconductor device. The semiconductor device includes a first transistor unit providing a first path of current and a second transistor unit designed in a mirror structure to the first transistor unit and providing a second path of current. The layout of the second transistor unit has a shape identical to the first transistor unit and shifted in a first direction. The layout of the semiconductor device reduces a mismatch of the transistors occurring when masks are combined, and thereby reduces their offset.