Current-Mirror Voltage Buffering for Slave VCDL Clock Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional buffer trimming methods for voltage controlled slaved clock circuits in master-slave systems are inefficient due to reliance on excessive analog circuitry and voltage accuracy, which are affected by design, process, voltage, and temperature fluctuations.
Innovation Solution
The use of current mirrors to provide high input/low output impedance buffers for generating master control voltage copies, combined with time-domain trimming approaches to adjust buffer characteristics, reducing the loading on the master clock circuitry and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional voltage domain buffer trimming methods are used, then buffer trimming functionality is provided, but excessive analog circuitry is required and voltage accuracy is compromised due to PVT fluctuations
Solution Approach 1:
The patent replaces the traditional voltage domain trimming method with a current domain approach. Current mirrors are used to replicate and distribute the control voltage to multiple slave VCDLs, eliminating the need for complex voltage domain trimming circuitry. The trimming is performed in the current domain by adjusting mirror current ratios, which is less sensitive to PVT fluctuations and requires simpler analog circuitry.
Solution Approach 2:
The patent changes the domain of operation from voltage to current for the trimming mechanism. By using current mirrors with adjustable current ratios, the system achieves accurate control voltage distribution without relying on precise voltage references or complex voltage trimming circuitry. The trimming is achieved by adjusting current parameters (mirror ratios) rather than voltage parameters.
2Reliability
If buffers are used to provide control voltages to slave circuits, then the master control voltage is isolated from loading effects, but buffer characteristics fluctuate due to design, process, voltage and temperature variations
Solution Approach 1:
The patent replaces traditional voltage buffers with current mirrors to distribute the control voltage. Current mirrors provide better isolation from loading effects and exhibit superior matching characteristics that are less sensitive to PVT variations. The current mirror topology inherently provides high input impedance and low output impedance, improving voltage stability without requiring additional buffer stages.
Solution Approach 2:
The patent implements a feedback mechanism where the control voltage is distributed through current mirrors to slave VCDLs, and the system monitors and adjusts the current mirror ratios to maintain accurate voltage distribution. This feedback approach compensates for buffer characteristic fluctuations and ensures consistent control voltage delivery to all slave circuits.
3Ease of manufacture
If voltage domain trimming methods are used, then buffer trimming is achieved, but the methods rely on voltage accuracy which is affected by design, process, voltage and temperature fluctuations
Solution Approach 1:
The patent substitutes voltage domain trimming with current domain trimming. Current mirrors provide inherent matching that is less sensitive to process and temperature variations. The trimming is achieved by adjusting current ratios in the mirrors, which can be implemented with simpler circuitry and provides more stable results under PVT fluctuations compared to voltage domain approaches.
Solution Approach 2:
The patent changes the trimming parameter from voltage to current. By adjusting current mirror ratios rather than voltage levels, the system achieves trimming functionality that is more robust to PVT variations. Current parameters can be adjusted with higher precision and stability, improving ease of manufacture and reducing sensitivity to environmental factors.
Data Source
AI summary
In some embodiments, disclosed herein are approaches for facilitating voltage controlled slaved (or replica) clock circuits such as voltage controlled delay lines (VCDLs) off of a master clock generator. In such systems, one or more control (or bias) voltages are generated to control a master clock generator such as a master DLL. One or more “slave” circuits may be controlled off of the master's control voltage so that their clocks replicate desired traits of the master clock.