Current-Mirror-Like Voltage Source for High-PSRR Chip Biasing
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Solution Overview
Problem
Conventional power designs on a chip face challenges in achieving a high power supply rejection ratio (PSRR) and suppressing power supply jitter (PSJ) due to the limitations of cascaded NMOS and PMOS transistors.
Innovation Solution
The introduction of a current-mirror-like voltage source structure, which includes a first and second n-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS) and an operational amplifier, operates in a saturation region to provide a load current with improved PSRR and reduced PSJ.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cascaded NMOS and PMOS transistors are used in conventional power design, then the power supply rejection ratio (PSRR) is improved, but power supply jitter (PSJ) is introduced and headroom is limited
Solution Approach 1:
The patent extracts the PMOS transistor from the conventional cascaded NMOS-PMOS structure and replaces it with a current-mirror-like voltage source consisting of two NMOS transistors and an operational amplifier. This extraction eliminates the PSJ introduction mechanism while maintaining PSRR improvement, as the new configuration uses only NMOS devices that do not introduce the same type of jitter.
Solution Approach 2:
The patent changes the operational parameters by biasing the operational amplifier with a higher voltage (Vdd2) than the main voltage source (Vdd1), allowing the NMOS transistors to operate in saturation region. This parameter change enables the voltage source to function as a high-impedance current source with improved PSRR while avoiding PSJ, achieving suppression below 1% threshold.
2Power
If cascaded NMOS and PMOS transistors are used, then power regulation is achieved, but headroom is shared and limited
Solution Approach 1:
The patent removes the PMOS transistor from the power regulation path, replacing it with a voltage source implemented using NMOS transistors. This extraction reduces the total number of series devices from three (NMOS-PMOS-voltage source) to two (voltage source-voltage source), thereby increasing the available headroom while maintaining full power regulation capability through the operational amplifier control.
3Object-generated harmful factors
If a charge pump and low-pass filter are added to suppress power supply jitter, then power supply jitter is reduced, but device complexity increases
Solution Approach 1:
The patent converts the operational amplifier's inherent voltage control capability into a benefit for PSJ suppression. By configuring the op-amp in a current-mirror-like voltage source arrangement with negative feedback, the circuit naturally filters high-frequency noise and jitter from the voltage source, achieving PSJ suppression below 1% without requiring separate charge pump and low-pass filter stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively suppresses power supply jitter to less than 1% and enhances the power supply rejection ratio, ensuring stable operation of the load current in the current-mirror-like voltage source.
Implementation Method 1
The operational amplifier, having an output terminal coupled to the gates of the first NMOS and the second NMOS has a negative input terminal coupled to a source of the first NMOS to form a negative feedback loop
Implementation Method 2
The charge pump pumps the first voltage source to the second voltage source
Implementation Method 3
The low-pass filter is coupled at an output terminal of the charge pump, to filter the second voltage source and to couple the filtered second voltage source to the operational amplifier
Implementation Method 4
The operational amplifier is powered by a second voltage source that is greater than the first voltage source, to operate the first NMOS and the second NMOS in their saturation region
Data Source
AI summary
A chip with a current-mirror-like voltage source is shown. The current-mirror-like voltage source has a first n-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS), a second NMOS, and an operational amplifier. The first and second NMOSs have drains coupled to a first voltage source Vdd1. The operational amplifier has an output terminal coupled to the gates of the first NMOS and the second NMOS, a negative input terminal coupled to the source of the first NMOS to form a negative feedback loop, and a positive input terminal coupled to the source of the second NMOS to form a positive feedback loop. The operational amplifier is powered by a second voltage source that is greater than the first voltage source, to operate the first and second NMOSs in their saturation region, and thereby the current-mirror-like voltage source outputs a load current mirrored from a first current.