Current-Mirror-Like Voltage Source for High-PSRR NMOS Biasing
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Solution Overview
Problem
Conventional power designs on a chip face challenges in achieving high power supply rejection ratio (PSRR) and suppressing power supply jitter (PSJ) due to the cascaded operation of NMOS and PMOS transistors, which limits the headroom and introduces jitter in the voltage supply.
Innovation Solution
The introduction of a current-mirror-like voltage source structure that includes a first and second n-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS) and an operational amplifier, operating in a saturation region with a negative and positive feedback loop, to provide a stable load current and suppress PSJ.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cascaded NMOS and PMOS transistors are used in conventional power design, then power supply rejection ratio (PSRR) is improved, but headroom is limited and power supply jitter (PSJ) is introduced
Solution Approach 1:
The patent extracts the PMOS transistor from the conventional cascaded NMOS-PMOS structure, replacing it with a current-mirror-like voltage source composed of two NMOS transistors and an operational amplifier. This removes the headroom limitation caused by the PMOS while maintaining PSRR improvement through the operational amplifier's feedback mechanism.
Solution Approach 2:
The patent changes the voltage source parameter from a fixed 1V supply to a dynamically regulated voltage generated by the operational amplifier. This allows the voltage to adapt to load conditions while maintaining sufficient headroom, eliminating the rigid headroom constraint of the conventional cascaded structure.
2Reliability
If cascaded NMOS and PMOS transistors are used, then regulated voltage is generated, but power supply jitter is introduced to the load
Solution Approach 1:
The operational amplifier implements a feedback mechanism by connecting its negative input terminal to the source of the first NMOS and its positive input terminal to the source of the second NMOS. This feedback loop actively suppresses power supply jitter by continuously adjusting the gate voltages to maintain stable output, reducing PSJ to less than 1% as stated in the technical effects.
3Reliability
If operational amplifier is powered by a second voltage source greater than the first voltage source, then NMOS transistors operate in saturation region, but additional voltage generation is required
Solution Approach 1:
The patent introduces a charge pump as an intermediary device that converts the first voltage source (VDD1) to the second voltage source (VDD2) required by the operational amplifier. This mediator component enables the NMOS transistors to operate in saturation region without requiring an external second voltage source, as the charge pump generates it internally from the available first voltage source.
Data Source
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AI summary
A chip with a current-mirror-like voltage source is shown. The current-mirror-like voltage source has a first n-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS), a second NMOS, and an operational amplifier. The first and second NMOSs have drains coupled to a first voltage source Vdd1. The operational amplifier has an output terminal coupled to the gates of the first NMOS and the second NMOS, a negative input terminal coupled to the source of the first NMOS to form a negative feedback loop, and a positive input terminal coupled to the source of the second NMOS to form a positive feedback loop. The operational amplifier is powered by a second voltage source that is greater than the first voltage source, to operate the first and second NMOSs in their saturation region, and thereby the current-mirror-like voltage source outputs a load current mirrored from a first current.