Current Mirror Wiring Layout for Thermal Strain Stability
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Solution Overview
Problem
In semiconductor integrated circuits, particularly current mirror circuits, thermal strain from wiring patterns causes variations in transistor pairing and circuit characteristics over time, especially in in-vehicle applications where temperature fluctuations are significant, leading to unreliable current control.
Innovation Solution
The solution involves arranging multiple MOS transistors with wiring layers such that the wiring patterns have the same shape within a predetermined range from the channel region of each transistor, including the use of dummy wiring to equalize thermal stress across transistors, thereby minimizing strain-induced changes in transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring patterns are arranged directly above MOS transistors to connect elements, then electrical connectivity is achieved, but thermal strain causes variation in transistor pairing characteristics over time
Solution Approach 1:
The patent extracts the harmful wiring patterns from directly above the transistor pairing regions. By removing or repositioning the wiring layers (particularly the first and second wiring layers) from overlapping with the transistors in plan view, the thermal strain caused by wiring is eliminated from the critical transistor pairing area, thereby maintaining stable transistor characteristics over time
Solution Approach 2:
The patent utilizes the vertical stacking dimension to resolve the wiring-transistor conflict. By arranging wiring layers in upper levels (third wiring layer and above) and configuring them to not overlap transistors in plan view, the design moves wiring away from the problematic two-dimensional plane, effectively separating the electrical connectivity function from the thermal strain source in the transistor region
2Reliability
If dummy wiring is added to equalize thermal stress, then transistor pairing stability improves, but device complexity increases
Solution Approach 1:
The patent merges the dummy wiring function with the actual wiring layers by configuring the third wiring layer and higher layers to serve both as functional interconnects and as thermal strain compensation structures. This integration eliminates the need for separate dummy wiring structures, achieving pairing consistency without proportionally increasing device complexity
Solution Approach 2:
The upper wiring layers (third layer and above) are designed to perform multiple functions: providing electrical connectivity between elements and simultaneously acting as thermal strain compensation structures by being positioned to overlap transistor regions in plan view. This multi-functionality reduces the need for additional dedicated dummy wiring, thereby limiting complexity increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures stable and reliable current control by equalizing thermal stress across MOS transistors, suppressing fluctuations in the mirror ratio over time and maintaining accurate circuit performance under varying temperature conditions.
Implementation Method 1
Due to the difference in the linear expansion coefficient between the metal films, the insulating films, and the semiconductor substrate, thermal strain may occur in the wiring pattern
Implementation Method 2
The current mirror circuit, which is often used in analog integrated circuits, converts the input current to a desired magnification (mirror ratio) according to the size of the MOS transistors on the input side and the output side
Data Source
AI summary
In a semiconductor device equipped with a current mirror circuit, a highly reliable semiconductor device capable of suppressing a change in a mirror ratio of the current mirror circuit over time is provided. A current mirror circuit that includes a first MOS transistor and a plurality of MOS transistors paired with the first MOS transistor, and a plurality of wiring layers formed on an upper layer of the MOS transistor are provided. The plurality of wiring layers are arranged such that wiring patterns have the same shape within a predetermined range from an end of a channel region of each of the first MOS transistor and the plurality of MOS transistors.