Current Mirroring for Non-Volatile Memory Cell Measurement

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Solution Overview

Problem

Conventional methods for measuring memory cell currents in non-volatile memory components are relatively inaccurate, which hinders precise determination of data bit states and optimal programming conditions.

Innovation Solution

A device and procedure that utilize current mirroring with p-MOS field-effect transistors to generate an analog current signal for precise measurement of memory cell currents, allowing for comparison with reference currents to determine data bit states and adjust programming parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional measurement methods are used for memory cell currents, then the measurement process is simple, but the measurement precision is relatively inaccurate

Engineering Contradiction:
Improvemeasurement precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary measurement path using p-MOS transistors (first and second p-MOS transistors) that mirror the memory cell current through a controlled voltage application. This intermediary structure allows accurate current measurement without directly interfering with the memory cell operation, resolving the contradiction between measurement precision and device complexity by adding a dedicated measurement pathway rather than modifying the core memory structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a current copy using the second p-MOS transistor that mirrors the memory cell current (Icell) to generate a measurable analog current signal (Imeasure). This copying mechanism allows precise measurement of the memory cell current without directly disturbing the original cell, achieving high measurement precision while maintaining relatively simple device architecture through current replication rather than direct measurement.

Inventive Principle:
Principle #26Copying

2Reliability

If conventional measurement methods are used, then the device structure remains simple, but the reliability of data bit determination is reduced

Engineering Contradiction:
ImprovereliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary measurement path using p-MOS transistors (first and second p-MOS transistors) that mirror the memory cell current through a controlled voltage application. This intermediary structure allows accurate current measurement without directly interfering with the memory cell operation, resolving the contradiction between measurement precision and device complexity by adding a dedicated measurement pathway rather than modifying the core memory structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the measured analog current signal is compared against reference currents to determine data bit states, and this information feeds back to adjust programming parameters. This feedback loop enhances reliability by enabling precise determination of data bit states and optimal adjustment of programming conditions, ensuring high reliability without requiring complex device modifications.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If conventional measurement methods are used, then the measurement process is straightforward, but the accuracy of programming conditions is compromised

Engineering Contradiction:
Improveprogramming precisionVSAvoiddevice complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the measured analog current signal is compared against reference currents to determine data bit states, and this information feeds back to adjust programming parameters. This feedback loop enhances reliability by enabling precise determination of data bit states and optimal adjustment of programming conditions, ensuring high reliability without requiring complex device modifications.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces an intermediary measurement path using p-MOS transistors (first and second p-MOS transistors) that mirror the memory cell current through a controlled voltage application. This intermediary structure allows accurate current measurement without directly interfering with the memory cell operation, resolving the contradiction between measurement precision and device complexity by adding a dedicated measurement pathway rather than modifying the core memory structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables precise measurement and adjustment of memory cell currents, improving the accuracy of data bit determination and programming conditions, reducing measurement uncertainties and enhancing the reliability of non-volatile memory components.

Implementation Method 1

current mirroring with p-MOS field-effect transistors to generate an analog current signal

Methodology Applied
Scientific EffectCurrent mirroring:

Data Source

PatentUS7379339B2Device and procedure for measuring memory cell currents
Publication Date: 2008.05.27 INFINEON TECHNOLOGIES AG
  • US7379339B2 patent drawing
  • US7379339B2 patent drawing
  • US7379339B2 patent drawing

AI summary

The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.